\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
DPWM Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODUFRQ : DPWM Modulation Frequency
bits : 0 - 2 (3 bit)
access : read-write
DEADTIME : DPWM Driver Deadtime Control
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
bits : 3 - 3 (1 bit)
access : read-write
DITHEREN : DPWM Signal Dither Control
To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither:
0: No dither.
1: ±1 bit dither
3: ±2 bit dither
bits : 4 - 5 (2 bit)
access : read-write
DPWMEN : DPWM Enable
0: Disable DPWM, SPK pins are tristate, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset).
1: Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO.
Note : This field will be effective only when DAC_EN field in this register is set as 0 .
bits : 6 - 6 (1 bit)
access : read-write
RXTHIE : DPWM FIFO Threshold Interrupt
0: DPWM FIFO threshold interrupt Disabled.
1: DPWM FIFO threshold interrupt Enabled.
bits : 8 - 8 (1 bit)
access : read-write
RXTH : DPWM FIFO Threshold
If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHF bit will set to 1, else the RXTHF bit will be cleared to 0.
bits : 9 - 12 (4 bit)
access : read-write
ZCIE : Zero Cross Enable
0: output data doesn't cross zero point
1: output data cross zero point
bits : 14 - 14 (1 bit)
access : read-write
DPWM Zero Order Hold Division Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZOH_DIV : DPWM Zero Order Hold, Down-sampling Divisor
The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register. Valid range is 1,..,255. Default is 48, which gives a sample rate of 13 kHz for a 39.936 MHz (default) HCLK.
bits : 0 - 7 (8 bit)
access : read-write
GAIN : (GAIN[7:0]+1)/256
bits : 8 - 15 (8 bit)
access : read-write
DPWM FIFO Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
RXTHF : DPWM FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH
End of enumeration elements list.
FIFO_POINTER : DPWM FIFO Pointer (Read Only)
The FULL bit and FIFO_POINTER[3:0] indicates the field that the valid data count within the DPWM FIFO buffer.
The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
bits : 3 - 6 (4 bit)
access : read-only
DPWM PDMA Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Enable DPWM DMA Interface
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA. No requests will be made to PDMA controller
#1 : 1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
End of enumeration elements list.
DPWM FIFO Input Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INDATA : DPWM FIFO Audio Data Input
A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
bits : 0 - 15 (16 bit)
access : write-only
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