Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
UART Receive/Transmit FIFO Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_8_bitReceived_TransmitData : Receive/Transmit FIFO Register
Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
By writing to this register, transmit data will be pushed onto the transmit FIFO. The UART will send out an 8-bit data through the Tx pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-write
UART Receiver Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_RST : Receiver Reset Write Only.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Write 1 to this bit, all the byte in the receive FIFO/ receive buffer and RX internal state machine are cleared
End of enumeration elements list.
RX_FULL : Receiver FIFO Full(Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receiver FIFO is not full
#1 : 1
Receiver FIFO is full
End of enumeration elements list.
RX_EMPTY : Receiver FIFO Empty(Read Only)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receiver FIFO is not empty
#1 : 1
Receiver FIFO is empty
End of enumeration elements list.
UART FIFO Threshold Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THD : Transmitter FIFO Threshold to Trigger Interrupt
If the valid data count of TX FIFO buffer is less than or equal to URTHD[2:0] threshold, it will generate an interrupt event flag and interrupt if enabled.
bits : 0 - 2 (3 bit)
access : read-write
RX_THD : Receiver FIFO Threshold to Trigger Interrupt
If the valid data count of RX FIFO buffer is more than or equal to URTHD[6:4] threshold, it will generate an interrupt event flag and interrupt if enabled.
bits : 4 - 6 (3 bit)
access : read-write
UART Interrupt Enable Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THD_IEN : Receive Data Available Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off TX_THD_INT
#1 : 1
Enable TX_THD_INT
End of enumeration elements list.
RX_THD_IEN : Transmit FIFO Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RX_THD_INT
#1 : 1
Enable RX_THD_INT
End of enumeration elements list.
RX_OVR_IEN : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RX_OVR_INT
#1 : 1
Enable RX_OVR_INT
End of enumeration elements list.
RX_BRK_IEN : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RX_BRK_INT
#1 : 1
Enable RX_BRK_INT
End of enumeration elements list.
RX_PARITY_IEN : Receive Time Out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RX_PARITY_INT
#1 : 1
Enable RX_PARITY_INT
End of enumeration elements list.
RX_FRAME_IEN : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RX_FRAME_INT
#1 : 1
Enable RX_FRAME_INT
End of enumeration elements list.
UART Interrupt Status Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THD_IF : Transmitter FIFO Threshold Interrupt Flag (Read Only)
This bit is set when the valid data count of TX FIFO buffer is less than or equal to URTHD[2:0] threshold. It will generate an interrupt if IER.TX_THD_IEN is enabled.
bits : 0 - 0 (1 bit)
access : read-only
RX_THD_IF : Receiver FIFO Threshold Interrupt Flag (Read Only)
This bit is set when the valid data count of RX FIFO buffer is more than or equal to URTHD[6:4] threshold. It will generate an interrupt if IER.RX_THD_IEN is enabled.
bits : 1 - 1 (1 bit)
access : read-only
RX_OVR_IF : Receiver Overrun Interrupt Flag (Set by H/W, Cleared by F/W Write 1 )
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver FIFO is not overflow
#1 : 1
Receiver FIFO is overflow. It will generate an interrupt if IER.RX_OVR_IEN is enabled
End of enumeration elements list.
RX_BRK_IF : Receiver Break Interrupt Flag (Set by H/W, Cleared by F/W Write 1 )
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No break in
#1 : 1
The receiver character is data bit = 0 , parity bit = 0 and no stop bit (stop bit=0) . It will generate an interrupt if IER.RX_OVR_IEN is enabled
End of enumeration elements list.
RX_PARITY_IF : Receiver Parity Error Interrupt Flag (Set by H/W, Cleared by F/W Write 1 )
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity error
#1 : 1
Parity error. It will generate an interrupt if IER.RX_PARITY_IEN is enabled
End of enumeration elements list.
RX_FRAME_IF : Receiver Frame Error Interrupt Flag (Set by H/W, Cleared by F/W Write 1 )
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No frame error
#1 : 1
Frame error (the receiver character has no valid stop bit). It will generate an interrupt if IER.RX_FRAME_IEN is enabled
End of enumeration elements list.
TX_THD_INT : Transmitter FIFO Threshold Interrupt Indicator to Interrupt Controller
Logical AND of IER.TX_THD_IEN and TX_THD_IF
bits : 8 - 8 (1 bit)
access : read-write
RX_THD_INT : Receiver FIFO Threshold Interrupt Indicator to Interrupt Controller
Logical AND of IER.RX_THD_IEN and RX_THD_IF
bits : 9 - 9 (1 bit)
access : read-write
RX_OVR_INT : Receiver Overrun Interrupt Indicator to Interrupt Controller
Logical AND of IER.RX_OVR_IEN and RX_OVR_IF
bits : 10 - 10 (1 bit)
access : read-write
RX_BRK_INT : Receiver Break Interrupt Indicator to Interrupt Controller
Logical AND of IER.RX_BRK_IEN and RX_BRK_IF
bits : 11 - 11 (1 bit)
access : read-write
RX_PARITY_INT : Receiver Parity Error Interrupt Indicator to Interrupt Controller
Logical AND of IER.RX_PARITY_IEN and RX_PARITY_IF
bits : 12 - 12 (1 bit)
access : read-write
RX_FRAME_INT : Receiver Frame Error Interrupt Indicator to Interrupt Controller
Logical AND of IER.RX_FRAME_IEN and RX_FRAME_IF
bits : 13 - 13 (1 bit)
access : read-write
UART Mode Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_BRK : ForceTXD Break
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Force TXD to 0
End of enumeration elements list.
PARITY_SEL : UART Mode Selection
If UMODE[3:2] is 00, no parity. UMODE[1] don't care.
Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Stop).
If UMODE[3:2] is not 00, with parity bit.
Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Parity, Stop).
UMODE[3:1] define parity bit.
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#010 : 2
ignore data whose parity is 1 if receiver (stick 0 parity if transmitter)
#011 : 3
ignore data whose parity is 0 if receiver (stick 1 parity if transmitter)
#100 : 4
even parity
#101 : 5
odd parity
#110 : 6
stick 0 parity
#111 : 7
stick 1 parity
End of enumeration elements list.
RX_EN : UART Receiver Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TX_EN : UART Transmitter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
UART Baud Rate Divisor Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR_DIV : UART Baud Rate Divider Register
Baud rate is determined by UART_CLK/16/( BR_DIV +1).
bits : 0 - 8 (9 bit)
access : read-write
TDLY : UART Transfer Delay Time Register
Define the transfer delay time between the last Stop bit and next Start bit in transmission.
bits : 16 - 19 (4 bit)
access : read-write
UART Transmitter Control and Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_RST : Transmit FIFO Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
Write 1 to this bit, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared
End of enumeration elements list.
TX_END : Transmit END(Read Only)
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The last transmit data is not completed
#1 : 1
The last transmit data is completed
End of enumeration elements list.
TX_FULL : Transmit FIFO Full(Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter FIFO is not full
#1 : 1
Transmitter FIFO is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Empty(Read Only)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter FIFO is not empty
#1 : 1
Transmitter FIFO is empty
End of enumeration elements list.
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