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ALED

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

ALED_CTL (CTL)

ALED_SLDAT (SLDAT)

ALED_DATA1 (DATA1)

ALED_DATA0 (DATA0)

ALED_SDTH (SDTH)


ALED_CTL (CTL)

ALED Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALED_CTL ALED_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALED_EN ALED_MODE DOUT_CTL ALED_T ALED_CLK FIFO_RST FIFO_FUL FIFO_EMP FIFO_FILL TX_END ALEDIF ALEDIE

ALED_EN : Enable Addressable LED 0: Disable addressable LED. 1: Enable addressable LED.
bits : 0 - 0 (1 bit)
access : read-write

ALED_MODE : Addressable LED Mode 0: 1-wire mode. 1: 2-wire mode.
bits : 1 - 1 (1 bit)
access : read-write

DOUT_CTL : Data Output Control 0: Stop data output. SDOUT or SDO/CKO keep in idle output. 1: Start data output from FIFO and continue output until FIFO is empty or ALED is disabled. If FIFO is empty, SDOUT or SDO/CKO keep in idle output. When FIFO is empty, user needs to decide to clear this bit or not.
bits : 2 - 2 (1 bit)
access : read-write

ALED_T : Addressable LED Data Transmission Method When Addressable LED Is Enabled 0: Low bit data sent at first 1: High bit data sent at first
bits : 3 - 3 (1 bit)
access : read-write

ALED_CLK : 2-wire Mode Clock Rate 00: clock rate is HIRC/4 01: clock rate is HIRC/8 10: clock rate is HIRC/16 11: clock rate is HIRC/32
bits : 4 - 5 (2 bit)
access : read-write

FIFO_RST : Reset FIFO 0: No operation This bit is write only.
bits : 8 - 8 (1 bit)
access : read-write

FIFO_FUL : FIFO Full Flag 0: FIFO is not full 1: FIFO is full, 16 bytes FIFO all are filled with data or the remaining FIFO quantity is less than valid FIFO size.
bits : 9 - 9 (1 bit)
access : read-write

FIFO_EMP : FIFO Empty Flag 0: FIFO is not empty 1: FIFO is empty
bits : 10 - 10 (1 bit)
access : read-write

FIFO_FILL : Valid Data Size Is Pushed Onto FIFO 00: Write ALED_SLDAT[7:0] to FIFO. 01: Write ALED_SLDAT[15:0] to FIFO. 10: Write ALED_SLDAT[23:0] to FIFO. 11: Write ALED_SLDAT[31:0] to FIFO.
bits : 11 - 12 (2 bit)
access : read-write

TX_END : Transmit END (Read Only) 0: 0: The last transmit data is not completed. 1: The last transmit data is completed.
bits : 13 - 13 (1 bit)
access : read

ALEDIF : ALED Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

It indicates that the FIFO buffer is more than ALED_SDTH[3:0] threshold. The interrupt flag is cleared to 0

#1 : 1

It indicates that the FIFO buffer is less than or equal to ALED_SDTH[3:0] threshold. The interrupt flag is set if ALED interrupt is enabled

End of enumeration elements list.

ALEDIE : ALED Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ALED Interrupt

#1 : 1

Enable ALED Interrupt

End of enumeration elements list.


ALED_SLDAT (SLDAT)

ALED Input Data
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALED_SLDAT ALED_SLDAT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLDAT

SLDAT : ALED Data A write to this register pushes data onto the FIFO and increments the write pointer.
bits : 0 - 31 (32 bit)
access : write-only


ALED_DATA1 (DATA1)

ALED Data1 Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALED_DATA1 ALED_DATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LODA1 HIDA1

LODA1 : Low Level Period of Data Bit 1 this Register Is Used Only in 1-wire Mode Low level period is LODA1[7:0]*(2/HIRC).
bits : 0 - 7 (8 bit)
access : read-write

HIDA1 : High Level Period of Data Bit 1 this Register Is Used Only in 1-wire Mode High level period is HIDA1[7:0]*(2/HIRC).
bits : 16 - 23 (8 bit)
access : read-write


ALED_DATA0 (DATA0)

ALED Data0 Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALED_DATA0 ALED_DATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LODA0 HIDA0

LODA0 : Low Level Period of Data Bit 0 this Register Is Used Only in 1-wire Mode Low level period is LODA0[7:0]*(2/HIRC).
bits : 0 - 7 (8 bit)
access : read-write

HIDA0 : High Level Period of Data Bit 0 this Register Is Used Only in 1-wire Mode High level period is HIDA0[7:0]*(2/HIRC).
bits : 16 - 23 (8 bit)
access : read-write


ALED_SDTH (SDTH)

ALED FIFO Threshold
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALED_SDTH ALED_SDTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDTH

SDTH : FIFO Threshold If ALED_CTL[0] is 1 and the valid data count of the FIFO buffer is less than or equal to ALED_SDTH[3:0] threshold, the ALED_CTL[30] will set to 1, else the ALED_CTL[30] will be cleared to 0.
bits : 0 - 3 (4 bit)
access : read-write



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