REGLOCK

OSCTRIM

OSC16K

GPA_INP

GPB_INP

GPA_ALT

GPB_ALT

RSTSRC

WAKECR

IPRSTC1

IPRSTC2

RegUnLock : Protected Register Unlock Register
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCTRIM0_TRIM : 8 Bit Trim For Oscillator TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
bits : 0 - 7 (8 bit)
access : read-write

OSCTRIM0_RANGE : Range Bit For Oscillator
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCTRIM1_TRIM : 8 Bit Trim For Oscillator TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
bits : 16 - 23 (8 bit)
access : read-write

OSCTRIM1_RANGE : Range Bit For Oscillator
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT16 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT17 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT18 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT19 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT20 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT21 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT22 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT23 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT24 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT25 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT26 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT27 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT28 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT29 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT30 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT31 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT16 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT17 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT18 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT19 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT20 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT21 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT22 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCHMITT23 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA0 : Alternate Function Setting For GPA1
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA1 : Alternate Function Setting For GPA2
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA2 : Alternate Function Setting For GPA3
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA3 : Alternate Function Setting For GPA3
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA4 : Alternate Function Setting For GPA4
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA5 : Alternate Function Setting For GPA5
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA6 : Alternate Function Setting For GPA6
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA7 : Alternate Function Setting For GPA7
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA8 : Alternate Function Setting For GPA8
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA9 : Alternate Function Setting For GPA9
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA10 : Alternate Function Setting For GPA10
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA11 : Alternate Function Setting For GPA11
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA12 : Alternate Function Setting For GPA12
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA13 : Alternate Function Setting For GPA13
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA14 : Alternate Function Setting For GPA14
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA15 : Alternate Function Setting For GPA15
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB0 : Alternate Function Setting For GPB0
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB1 : Alternate Function Setting For GPB1
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB2 : Alternate Function Setting For GPB2
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB3 : Alternate Function Setting For GPB3
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB4 : Alternate Function Setting For GPB4
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB5 : Alternate Function Setting For GPB5
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB6 : Alternate Function Setting For GPB6
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB7 : Alternate Function Setting For GPB7
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CORE : Reset Source From CORE The RSTS_CORE flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset. This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDG : Reset Source From WDG The RSTS_WDG flag is set if pervious reset source originates from the Watch-Dog module. This bit is cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_SYS : Reset Source From MCU The RSTS_SYS flag is set if the previous reset source originates from the Cortex_M0 kernel. This bit is cleared by writing 1 to itself.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_PMU : Reset Source From PMU The RSTS_PMU flag is set if the PMU. This bit is cleared by writing 1 to itself.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : Reset Source From CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTCR1[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit is cleared by writing 1 to itself.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_DIN : State Of Wakeup Pin Read only.
bits : 0 - 0 (1 bit)
access : read-write

WAKE_TRI : Wakeup Pin Pull-up Control This signal is latched in deep power down and preserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_OENB : Wakeup Pin Output Enable Bar
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_DOUT : Wakeup Output State
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIP_RST : CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles. CHIP_RST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (REGLOCK))
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (REGLOCK))
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_RST : PDMA Controller Reset Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWM_RST : DPWM Speaker Driver Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIQ_RST : Biquad Filter Block Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_RST : CRC Generation Block Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM10_RST : PWM10 controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_RST : Analog Comparator Reset
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_RST : I2S Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANA_RST : Analog Block Control Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.