CON

CLK

TOC

ADDR1

ADDR2

ADDR3

ADM0

ADM1

ADM2

ADM3

ADDR0

DATA

STATUS

AA : Assert Acknowledge Control Bit 1. A slave is acknowledging the address sent from master, 2. The receiver devices are acknowledging the data sent by transmitter. When AA = 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag When a new SIO state is present in the I2C->STATUS register, the SI flag is set by hardware, and if bit EI (I2C->CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control Bit In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control Bit Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

ENSI : I2C Controller Enable Bit Set to enable I2C serial function block.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EI : Enable Interrupt
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK : I2C Clock Divided Register The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2C->CLK+1)).
bits : 0 - 7 (8 bit)
access : read-write

TIF : Time-Out Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV4 : Time-Out Counter Input Clock Divide By 4 When enabled, the time-out clock is PCLK/4.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENTI : Time-out Counter Control Bit When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx1 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx2 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx3 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx4 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx5 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx6 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMx7 : I2C Address Mask register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched.
bits : 1 - 7 (7 bit)
access : read-write

DATA : I2C Data Register During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status Register The status register of I2C: The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2C->STATUS contains F8H, no serial interrupt is requested. All other I2C->STATUS values correspond to defined I2C states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in I2C->STATUS one PCLK cycle after SI is set by hardware and is still present one PCLK cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
bits : 0 - 7 (8 bit)
access : read-only