PPR

CMR0

PDR0

CNR1

CMR1

PDR1

CSR

PIER

PIFR

CCR0

CRLR0

CFLR0

CRLR1

CFLR1

CAPENR

POE

PCR

CNR0

CP01 : Clock Pre-scaler Clock input is divided by (CP01 + 1). If CP01 = 0, then the pre-scaler output clock will be stopped. This implies PWM counter 0 and 1 will also be stopped.
bits : 0 - 7 (8 bit)
access : read-write

DZI01 : Dead Zone Interval Register For Pair Of PWM0 And PWM1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write

CMR : PWM Comparator Register CMR determines the PWM duty cycle. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1) Duty Cycle = (CMR+1)/(CNR+1). CMR > = CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register Reports the current value of the 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CSR0 : Timer 0 Clock Source Selection (Table is as CSR1)
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : Timer 1 Clock Source Selection Value : Input clock divided by 0 : 2 1 : 4 2 : 8 3 : 16 4 : 1
bits : 4 - 6 (3 bit)
access : read-write

PWMIE0 : PWM Timer 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE1 : PWM Timer 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIF0 : PWM Timer 0 Interrupt Flag Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

PWMIF1 : PWM Timer 1 Interrupt Flag Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

INV0 : Channel 0 Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Capture Channel 0 transition Enable/Disable When enabled, Capture function latches the PMW-counter to CRLR (Rising latch) and CFLR (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt is enabled (CRL_IE0 = 1), a rising transition at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFL_IE0 = 1). This flag is cleared by software writing a '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : CRLR0 Latched Indicator Bit When input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : CFLR0 Latched Indicator Bit When input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : Channel 1 Inverter ON/OFF
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable When enabled, capture block generates an interrupt on rising edge of input.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable When enabled, capture block generates an interrupt on falling edge of input.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Capture Channel 1 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to CRLR (Rising latch) and CFLR (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt is enabled (CRL_IE1 = 1), a rising transition at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFL_IE1 = 1). This flag is cleared by software writing a '1' to it.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator Bit When input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator Bit When input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 23 - 23 (1 bit)
access : read-write

CRLR : Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

CAPENR : Capture Input Enable Register 0 : OFF (GPA[13:12] pin input disconnected from Capture block) 1 : ON (GPA[13:12] pin, if in PWM alternative function, will be configured as an input and fed to capture function) CAPENR[1:0] Bit 10 Bit x1 : Capture channel 0 is from GPA [12] Bit 1x : Capture channel 1 is from GPA [13]
bits : 0 - 3 (4 bit)
access : read-write

PWM0 : PWM0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPA_ALT Table 57)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : PWM1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPA_ALT Table 57)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : PWM-Timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-Timer 0 Output Inverter ON/OFF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause CNR0 and CMR0 to be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-Zone 0 Generator Enable/Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 become a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-Timer 1 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-Timer 1 Output Inverter ON/OFF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-Timer 1 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause CNR1 and CMR1 to be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNR : PWM Counter/Timer Reload Value CNR determines the PWM period. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1) Duty ratio = (CMR+1)/(CNR+1). CMR > = CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit PWM high width = 1 unit (Unit = one PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write