CSRn

POINTn

CSARn

CDARn

CBCRn

IERn

ISRn

SARn

DARn

BCRn

PDMACEN : PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE_SEL : PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are:
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAD_SEL : Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAD_SEL : Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRA_INT_SEL : Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BCR = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BCR = 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated.
bits : 12 - 15 (4 bit)
access : read-write

APB_TWS : Peripheral Transfer Width Select This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIG_EN : Trigger Enable - Start a PDMA operation Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POINT : PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
bits : 0 - 3 (4 bit)
access : read-only

CSAR : PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only

CDAR : PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only

CBCR : PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKD_IE : PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAR_IE : Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WRA_INT_SEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TABORT_IF : PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKD_IF : Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAR_IF : Wrap Around Transfer Byte Count Interrupt Flag These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 0001 = Current transfer finished flag (CBCR == 0). 0100 = Current transfer half complete flag (CBCR == BCR/2).
bits : 8 - 11 (4 bit)
access : read-write

INTR : Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel.
bits : 31 - 31 (1 bit)
access : read-only

SAR : PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write

DAR : PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write

BCR : PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: When in memory-to-memory (CSR.MODE_SEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes.
bits : 0 - 15 (16 bit)
access : read-write