Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :
Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable the ADC module.
1 : EN
Enable the ADC module.
End of enumeration elements list.
TMPSPWR : This enables power to the temperature sensor module. After setting this bit, the temperature sensor will remain powered down while the ADC is power is disconnected (i.e, when the ADC PWDSTAT is 2'b10).
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : DIS
Power down the temperature sensor.
1 : EN
Enable the temperature sensor when the ADC is in it's active state.
End of enumeration elements list.
RPTEN : This bit enables Repeating Scan Mode.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : SINGLE_SCAN
In Single Scan Mode, the ADC will complete a single scan upon each trigger event.
1 : REPEATING_SCAN
In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled.
End of enumeration elements list.
LPMODE : Select power mode to enter between active scans.
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
0 : MODE0
Low Power Mode 0 (2'b00). Leaves the ADC fully powered between scans with no latency between a trigger event and sample data collection.
1 : MODE1
Low Power Mode 1 (2'b01). Enables a low power mode for the ADC between scans requiring 50us initialization time (latency) between a trigger event and the scan (assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required).
2 : MODE2
Low Power Mode 2 (2'b10). Disconnects power and clocks to the ADC effectively eliminating all active power associated with the ADC between scans. This mode requires 150us initialization (again, assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required).
3 : MODE_UNDEFINED
Undefined Mode (2'b11)
End of enumeration elements list.
OPMODE : Select the sample rate mode. It adjusts the current in the ADC for higher sample rates. A 12MHz ADC clock can result in a sample rate up to 1Msps depending on the trigger or repeating mode rate. A 1.5MHz ADC clock can result in a sample rate up 125K sps. NOTE: All other values not specified below are undefined.
bits : 5 - 11 (7 bit)
access : read-write
Enumeration:
0 : SAMPLE_RATE_LE_125KSPS
Sample Rate <= 125K sps
2 : SAMPLE_RATE_125K_1MSPS
Sample Rate 125K to 1M sps
End of enumeration elements list.
BATTLOAD : Control 500 Ohm battery load resistor.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : DIS
Disable battery load.
1 : EN
Enable battery load.
End of enumeration elements list.
REFSEL : Select the ADC reference voltage.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : INTERNAL
Internal Bandgap Reference Voltage
1 : VDD
Select VDD as the ADEC reference voltage.
2 : ADCREF
Off Chip Reference (ADC_REF)
3 : UNDEFINED
Reserved
End of enumeration elements list.
TRIGSEL : Select the ADC trigger source.
bits : 16 - 35 (20 bit)
access : read-write
Enumeration:
0 : EXT0
Off chip External Trigger0 (ADC_ET0)
1 : EXT1
Off chip External Trigger1 (ADC_ET1)
2 : EXT2
Off chip External Trigger2 (ADC_ET2)
3 : EXT3
Off chip External Trigger3 (ADC_ET3)
4 : EXT4
Off chip External Trigger4 (ADC_ET4)
5 : EXT5
Off chip External Trigger5 (ADC_ET5)
6 : EXT6
Off chip External Trigger6 (ADC_ET6)
7 : EXT7
Off chip External Trigger7 (ADC_ET7)
8 : SWT
Software Trigger
End of enumeration elements list.
TRIGPOL : This bit selects the ADC trigger polarity for external off chip triggers.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Trigger on rising edge.
1 : FALLING_EDGE
Trigger on falling edge.
End of enumeration elements list.
CLKSEL : Select the source and frequency for the ADC clock. All values not enumerated below are undefined.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : OFF
Low Power Mode.
1 : 12MHZ
12 MHz ADC clock.
2 : 6MHZ
6 MHz ADC clock.
3 : 3MHZ
12 MHz ADC clock.
4 : 1_5MHZ
1.5 MHz ADC clock.
End of enumeration elements list.
Slot 1 Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN1 : This bit enables slot 1 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 1 for ADC conversions.
End of enumeration elements list.
WCEN1 : This bit enables the window compare function for slot 1.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 1.
End of enumeration elements list.
CHSEL1 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL1 : Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5 Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL1 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Slot 2 Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN2 : This bit enables slot 2 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 2 for ADC conversions.
End of enumeration elements list.
WCEN2 : This bit enables the window compare function for slot 2.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 2.
End of enumeration elements list.
CHSEL2 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL2 : Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL2 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Slot 3 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN3 : This bit enables slot 3 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 3 for ADC conversions.
End of enumeration elements list.
WCEN3 : This bit enables the window compare function for slot 3.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 3.
End of enumeration elements list.
CHSEL3 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL3 : Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL3 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Slot 4 Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN4 : This bit enables slot 4 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 4 for ADC conversions.
End of enumeration elements list.
WCEN4 : This bit enables the window compare function for slot 4.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 4.
End of enumeration elements list.
CHSEL4 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL4 : Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL4 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Slot 5 Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN5 : This bit enables slot 5 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 5 for ADC conversions.
End of enumeration elements list.
WCEN5 : This bit enables the window compare function for slot 5.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 5.
End of enumeration elements list.
CHSEL5 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL5 : Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL5 : Select number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
ADC Interrupt registers: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCMP : ADC conversion complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CNVCMPINT
ADC conversion complete interrupt.
End of enumeration elements list.
SCNCMP : ADC scan complete interrupt.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : SCNCMPINT
ADC scan complete interrupt.
End of enumeration elements list.
FIFOOVR1 : FIFO 75 percent full interrupt.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : FIFO75INT
FIFO 75 percent full interrupt.
End of enumeration elements list.
FIFOOVR2 : FIFO 100 percent full interrupt.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : FIFOFULLINT
FIFO 100 percent full interrupt.
End of enumeration elements list.
WCEXC : Window comparator voltage excursion interrupt.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : WCEXCINT
Window comparitor voltage excursion interrupt.
End of enumeration elements list.
WCINC : Window comparator voltage incursion interrupt.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : WCINCINT
Window comparitor voltage incursion interrupt.
End of enumeration elements list.
ADC Interrupt registers: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCMP : ADC conversion complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CNVCMPINT
ADC conversion complete interrupt.
End of enumeration elements list.
SCNCMP : ADC scan complete interrupt.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : SCNCMPINT
ADC scan complete interrupt.
End of enumeration elements list.
FIFOOVR1 : FIFO 75 percent full interrupt.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : FIFO75INT
FIFO 75 percent full interrupt.
End of enumeration elements list.
FIFOOVR2 : FIFO 100 percent full interrupt.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : FIFOFULLINT
FIFO 100 percent full interrupt.
End of enumeration elements list.
WCEXC : Window comparator voltage excursion interrupt.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : WCEXCINT
Window comparitor voltage excursion interrupt.
End of enumeration elements list.
WCINC : Window comparator voltage incursion interrupt.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : WCINCINT
Window comparitor voltage incursion interrupt.
End of enumeration elements list.
ADC Interrupt registers: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCMP : ADC conversion complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CNVCMPINT
ADC conversion complete interrupt.
End of enumeration elements list.
SCNCMP : ADC scan complete interrupt.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : SCNCMPINT
ADC scan complete interrupt.
End of enumeration elements list.
FIFOOVR1 : FIFO 75 percent full interrupt.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : FIFO75INT
FIFO 75 percent full interrupt.
End of enumeration elements list.
FIFOOVR2 : FIFO 100 percent full interrupt.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : FIFOFULLINT
FIFO 100 percent full interrupt.
End of enumeration elements list.
WCEXC : Window comparator voltage excursion interrupt.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : WCEXCINT
Window comparitor voltage excursion interrupt.
End of enumeration elements list.
WCINC : Window comparator voltage incursion interrupt.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : WCINCINT
Window comparitor voltage incursion interrupt.
End of enumeration elements list.
ADC Interrupt registers: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNVCMP : ADC conversion complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CNVCMPINT
ADC conversion complete interrupt.
End of enumeration elements list.
SCNCMP : ADC scan complete interrupt.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : SCNCMPINT
ADC scan complete interrupt.
End of enumeration elements list.
FIFOOVR1 : FIFO 75 percent full interrupt.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : FIFO75INT
FIFO 75 percent full interrupt.
End of enumeration elements list.
FIFOOVR2 : FIFO 100 percent full interrupt.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : FIFOFULLINT
FIFO 100 percent full interrupt.
End of enumeration elements list.
WCEXC : Window comparator voltage excursion interrupt.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : WCEXCINT
Window comparitor voltage excursion interrupt.
End of enumeration elements list.
WCINC : Window comparator voltage incursion interrupt.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : WCINCINT
Window comparitor voltage incursion interrupt.
End of enumeration elements list.
Slot 6 Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN6 : This bit enables slot 6 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 6 for ADC conversions.
End of enumeration elements list.
WCEN6 : This bit enables the window compare function for slot 6.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 6.
End of enumeration elements list.
CHSEL6 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL6 : Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL6 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Slot 7 Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN7 : This bit enables slot 7 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 7 for ADC conversions.
End of enumeration elements list.
WCEN7 : This bit enables the window compare function for slot 7.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 7.
End of enumeration elements list.
CHSEL7 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL7 : Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL7 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
Window Comparator Limits Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LLIM : Sets the lower limit for the wondow comparator.
bits : 0 - 15 (16 bit)
access : read-write
ULIM : Sets the upper limit for the wondow comparator.
bits : 16 - 47 (32 bit)
access : read-write
FIFO Data and Valid Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Oldest data in the FIFO.
bits : 0 - 15 (16 bit)
access : read-write
COUNT : Number of valid entries in the ADC FIFO.
bits : 16 - 35 (20 bit)
access : read-write
RSVD_20 : RESERVED.
bits : 20 - 43 (24 bit)
access : read-write
SLOTNUM : Slot number associated with this FIFO data.
bits : 24 - 50 (27 bit)
access : read-write
RSVD_27 : RESERVED.
bits : 27 - 58 (32 bit)
access : read-write
ADC Power Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWDSTAT : Indicates the power-status of the ADC.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ON
Powered on.
1 : SWITCH_ON_SAR_OFF
Power switch on, ADC Low Power Mode 1.
2 : POWER_SWITCH_OFF
Power switch off, ADC disabled.
End of enumeration elements list.
Software trigger
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWT : Writing 0x37 to this register generates a software trigger.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
55 : GEN_SW_TRIGGER
Writing this value generates a software trigger.
End of enumeration elements list.
Slot 0 Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEN0 : This bit enables slot 0 for ADC conversions.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : SLEN
Enable slot 0 for ADC conversions.
End of enumeration elements list.
WCEN0 : This bit enables the window compare function for slot 0.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : WCEN
Enable the window compare for slot 0.
End of enumeration elements list.
CHSEL0 : Select one of the 13 channel inputs for this slot.
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
0 : EXT0
ADC_EXT0 external GPIO pin connection.
1 : EXT1
ADC_EXT1 external GPIO pin connection.
2 : EXT2
ADC_EXT2 external GPIO pin connection.
3 : EXT3
ADC_EXT3 external GPIO pin connection.
4 : EXT4
ADC_EXT4 external GPIO pin connection.
5 : EXT5
ADC_EXT5 external GPIO pin connection.
6 : EXT6
ADC_EXT6 external GPIO pin connection.
7 : EXT7
ADC_EXT7 external GPIO pin connection.
8 : TEMP
ADC_TEMP internal temperature sensor.
9 : VDD
ADC_VDD internal power rail connection.
10 : VSS
ADC_VSS internal ground connection.
12 : VBATT
ADC_VBATT internal voltage divide-by-3 connection to input power rail.
End of enumeration elements list.
THSEL0 : Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
bits : 16 - 34 (19 bit)
access : read-write
Enumeration:
0 : 1_ADC_CLK
1 ADC clock cycle.
1 : 2_ADC_CLKS
2 ADC clock cycles.
2 : 4_ADC_CLKS
4 ADC clock cycles.
3 : 8_ADC_CLKS
8 ADC clock cycles.
4 : 16_ADC_CLKS
16 ADC clock cycles.
5 : 32_ADC_CLKS
32 ADC clock cycles.
6 : 64_ADC_CLKS
64 ADC clock cycles.
7 : 128_ADC_CLKS
128 ADC clock cycles.
End of enumeration elements list.
ADSEL0 : Select the number of measurements to average in the accumulate divide module for this slot.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : AVG_1_MSRMT
Average in 1 measurement in the accumulate divide module for this slot.
1 : AVG_2_MSRMTS
Average in 2 measurements in the accumulate divide module for this slot.
2 : AVG_4_MSRMTS
Average in 4 measurements in the accumulate divide module for this slot.
3 : AVG_8_MSRMT
Average in 8 measurements in the accumulate divide module for this slot.
4 : AVG_16_MSRMTS
Average in 16 measurements in the accumulate divide module for this slot.
5 : AVG_32_MSRMTS
Average in 32 measurements in the accumulate divide module for this slot.
6 : AVG_64_MSRMTS
Average in 64 measurements in the accumulate divide module for this slot.
7 : AVG_128_MSRMTS
Average in 128 measurements in the accumulate divide module for this slot.
End of enumeration elements list.
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