Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :
Counter/Timer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA0 : Counter/Timer A0.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB0 : Counter/Timer B0.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA1 : Counter/Timer A1.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB1 : Counter/Timer B1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer A1 Compare Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A1 : Counter/Timer A1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A1 : Counter/Timer A1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B1 Compare Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B1 : Counter/Timer B1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B1 : Counter/Timer B1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA1EN : Counter/Timer A1 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A1 Disable.
1 : EN
Counter/Timer A1 Enable.
End of enumeration elements list.
TMRA1CLK : Counter/Timer A1 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is the HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream A.
End of enumeration elements list.
TMRA1FN : Counter/Timer A1 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A1, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA1IE : Counter/Timer A1 Interrupt Enable bit.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A1 from generating an interrupt.
1 : EN
Enable counter/timer A1 to generate an interrupt.
End of enumeration elements list.
TMRA1PE : Counter/Timer A1 Output Enable bit.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA1POL.
1 : EN
Enable counter/timer A1 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRA1CLR : Counter/Timer A1 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A1 to run
1 : CLEAR
Holds counter/timer A1 at 0x0000.
End of enumeration elements list.
TMRA1POL : Counter/Timer A1 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA1 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA1 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB1EN : Counter/Timer B1 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B1 Disable.
1 : EN
Counter/Timer B1 Enable.
End of enumeration elements list.
TMRB1CLK : Counter/Timer B1 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream B.
End of enumeration elements list.
TMRB1FN : Counter/Timer B1 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B1, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB1IE : Counter/Timer B1 Interrupt Enable bit.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B1 from generating an interrupt.
1 : EN
Enable counter/timer B1 to generate an interrupt.
End of enumeration elements list.
TMRB1PE : Counter/Timer B1 Output Enable bit.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB1POL.
1 : EN
Enable counter/timer B1 to generate a signal on TMRPINB.
End of enumeration elements list.
TMRB1CLR : Counter/Timer B1 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B1 to run
1 : CLEAR
Holds counter/timer B1 at 0x0000.
End of enumeration elements list.
TMRB1POL : Counter/Timer B1 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB1 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB1 pin is the inverse of the timer output.
End of enumeration elements list.
CTLINK1 : Counter/Timer A1/B1 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A0/B0 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A1/B1 timers into a single 32-bit timer.
End of enumeration elements list.
Counter/Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA2 : Counter/Timer A2.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB2 : Counter/Timer B2.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0INT : Counter/Timer A0 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0INT : Counter/Timer B0 interrupt.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1INT : Counter/Timer A1 interrupt.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1INT : Counter/Timer B1 interrupt.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2INT : Counter/Timer A2 interrupt.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2INT : Counter/Timer B2 interrupt.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3INT : Counter/Timer A3 interrupt.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3INT : Counter/Timer B3 interrupt.
bits : 7 - 14 (8 bit)
access : read-write
Counter/Timer Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0INT : Counter/Timer A0 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0INT : Counter/Timer B0 interrupt.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1INT : Counter/Timer A1 interrupt.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1INT : Counter/Timer B1 interrupt.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2INT : Counter/Timer A2 interrupt.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2INT : Counter/Timer B2 interrupt.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3INT : Counter/Timer A3 interrupt.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3INT : Counter/Timer B3 interrupt.
bits : 7 - 14 (8 bit)
access : read-write
Counter/Timer Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0INT : Counter/Timer A0 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0INT : Counter/Timer B0 interrupt.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1INT : Counter/Timer A1 interrupt.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1INT : Counter/Timer B1 interrupt.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2INT : Counter/Timer A2 interrupt.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2INT : Counter/Timer B2 interrupt.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3INT : Counter/Timer A3 interrupt.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3INT : Counter/Timer B3 interrupt.
bits : 7 - 14 (8 bit)
access : read-write
Counter/Timer Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0INT : Counter/Timer A0 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0INT : Counter/Timer B0 interrupt.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1INT : Counter/Timer A1 interrupt.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1INT : Counter/Timer B1 interrupt.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2INT : Counter/Timer A2 interrupt.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2INT : Counter/Timer B2 interrupt.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3INT : Counter/Timer A3 interrupt.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3INT : Counter/Timer B3 interrupt.
bits : 7 - 14 (8 bit)
access : read-write
Counter/Timer A2 Compare Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A2 : Counter/Timer A2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A2 : Counter/Timer A2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B2 Compare Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B2 : Counter/Timer B2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B2 : Counter/Timer B2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA2EN : Counter/Timer A2 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A2 Disable.
1 : EN
Counter/Timer A2 Enable.
End of enumeration elements list.
TMRA2CLK : Counter/Timer A2 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream B.
End of enumeration elements list.
TMRA2FN : Counter/Timer A2 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A2, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA2IE : Counter/Timer A2 Interrupt Enable bit.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A2 from generating an interrupt.
1 : EN
Enable counter/timer A2 to generate an interrupt.
End of enumeration elements list.
TMRA2PE : Counter/Timer A2 Output Enable bit.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA2POL.
1 : EN
Enable counter/timer A2 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRA2CLR : Counter/Timer A2 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A2 to run
1 : CLEAR
Holds counter/timer A2 at 0x0000.
End of enumeration elements list.
TMRA2POL : Counter/Timer A2 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA2 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA2 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB2EN : Counter/Timer B2 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B2 Disable.
1 : EN
Counter/Timer B2 Enable.
End of enumeration elements list.
TMRB2CLK : Counter/Timer B2 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream A.
End of enumeration elements list.
TMRB2FN : Counter/Timer B2 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B2, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB2IE : Counter/Timer B2 Interrupt Enable bit.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B2 from generating an interrupt.
1 : EN
Enable counter/timer B2 to generate an interrupt.
End of enumeration elements list.
TMRB2PE : Counter/Timer B2 Output Enable bit.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB2POL.
1 : EN
Enable counter/timer B2 to generate a signal on TMRPINB.
End of enumeration elements list.
TMRB2CLR : Counter/Timer B2 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B2 to run
1 : CLEAR
Holds counter/timer B2 at 0x0000.
End of enumeration elements list.
TMRB2POL : Counter/Timer B2 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB2 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB2 pin is the inverse of the timer output.
End of enumeration elements list.
CTLINK2 : Counter/Timer A2/B2 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A0/B0 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A2/B2 timers into a single 32-bit timer.
End of enumeration elements list.
Counter/Timer Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA3 : Counter/Timer A3.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB3 : Counter/Timer B3.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer A3 Compare Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A3 : Counter/Timer A3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A3 : Counter/Timer A3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B3 Compare Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B3 : Counter/Timer B3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B3 : Counter/Timer B3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA3EN : Counter/Timer A3 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A3 Disable.
1 : EN
Counter/Timer A3 Enable.
End of enumeration elements list.
TMRA3CLK : Counter/Timer A3 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream B.
End of enumeration elements list.
TMRA3FN : Counter/Timer A3 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A3, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA3IE : Counter/Timer A3 Interrupt Enable bit.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A3 from generating an interrupt.
1 : EN
Enable counter/timer A3 to generate an interrupt.
End of enumeration elements list.
TMRA3PE : Counter/Timer A3 Output Enable bit.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA3POL.
1 : EN
Enable counter/timer A3 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRA3CLR : Counter/Timer A3 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : CLEAR
Holds counter/timer A3 at 0x0000.
End of enumeration elements list.
TMRA3POL : Counter/Timer A3 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA3 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA3 pin is the inverse of the timer output.
End of enumeration elements list.
ADCEN : Special Timer A3 enable for ADC function.
bits : 15 - 30 (16 bit)
access : read-write
TMRB3EN : Counter/Timer B3 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B3 Disable.
1 : EN
Counter/Timer B3 Enable.
End of enumeration elements list.
TMRB3CLK : Counter/Timer B3 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream A.
End of enumeration elements list.
TMRB3FN : Counter/Timer B3 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B3, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB3IE : Counter/Timer B3 Interrupt Enable bit.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B3 from generating an interrupt.
1 : EN
Enable counter/timer B3 to generate an interrupt.
End of enumeration elements list.
TMRB3PE : Counter/Timer B3 Output Enable bit.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB3POL.
1 : EN
Enable counter/timer B3 to generate a signal on TMRPINB.
End of enumeration elements list.
TMRB3CLR : Counter/Timer B3 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B3 to run.
1 : CLEAR
Holds counter/timer B3 at 0x0000.
End of enumeration elements list.
TMRB3POL : Counter/Timer B3 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB3 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB3 pin is the inverse of the timer output.
End of enumeration elements list.
CTLINK3 : Counter/Timer A/B Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A0/B0 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A3/B3 timers into a single 32-bit timer.
End of enumeration elements list.
Counter/Timer A0 Compare Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A0 : Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A0 : Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B0 Compare Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B0 : Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B0 : Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA0EN : Counter/Timer A0 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A0 Disable.
1 : EN
Counter/Timer A0 Enable.
End of enumeration elements list.
TMRA0CLK : Counter/Timer A0 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream A.
End of enumeration elements list.
TMRA0FN : Counter/Timer A0 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A0, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA0IE : Counter/Timer A0 Interrupt Enable bit.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A0 from generating an interrupt.
1 : EN
Enable counter/timer A0 to generate an interrupt.
End of enumeration elements list.
TMRA0PE : Counter/Timer A0 Output Enable bit.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA0POL.
1 : EN
Enable counter/timer B0 to generate a signal on TMRPINB.
End of enumeration elements list.
TMRA0CLR : Counter/Timer A0 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A0 to run
1 : CLEAR
Holds counter/timer A0 at 0x0000.
End of enumeration elements list.
TMRA0POL : Counter/Timer A0 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA0 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA0 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB0EN : Counter/Timer B0 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B0 Disable.
1 : EN
Counter/Timer B0 Enable.
End of enumeration elements list.
TMRB0CLK : Counter/Timer B0 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC
Clock source is the HFRC
2 : HFRC_DIV8
Clock source is HFRC / 8
3 : HFRC_DIV128
Clock source is HFRC / 128
4 : HFRC_DIV512
Clock source is HFRC / 512
5 : HFRC_DIV2K
Clock source is HFRC / 2048
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC / 16K
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream B.
End of enumeration elements list.
TMRB0FN : Counter/Timer B0 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B0, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB0IE : Counter/Timer B0 Interrupt Enable bit.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B0 from generating an interrupt.
1 : EN
Enable counter/timer B0 to generate an interrupt.
End of enumeration elements list.
TMRB0PE : Counter/Timer B0 Output Enable bit.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB0POL.
1 : EN
Enable counter/timer B0 to generate a signal on TMRPINB.
End of enumeration elements list.
TMRB0CLR : Counter/Timer B0 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B0 to run
1 : CLEAR
Holds counter/timer B0 at 0x0000.
End of enumeration elements list.
TMRB0POL : Counter/Timer B0 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB0 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB0 pin is the inverse of the timer output.
End of enumeration elements list.
CTLINK0 : Counter/Timer A0/B0 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A0/B0 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A0/B0 timers into a single 32-bit timer.
End of enumeration elements list.
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