\n
address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :
FIFO Access Port
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO access port.
bits : 0 - 31 (32 bit)
access : read-write
Current FIFO Pointers
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOSIZ : The number of bytes currently in the FIFO.
bits : 0 - 6 (7 bit)
access : read-write
FIFOREM : The number of bytes remaining in the FIFO (i.e. 64-FIFOSIZ).
bits : 16 - 38 (23 bit)
access : read-write
Transfer Length
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLNGTH : Remaining transfer length.
bits : 0 - 11 (12 bit)
access : read-write
FIFO Threshold Configuration
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFORTHR : FIFO read threshold.
bits : 0 - 5 (6 bit)
access : read-write
FIFOWTHR : FIFO write threshold.
bits : 8 - 21 (14 bit)
access : read-write
I/O Clock Configuration
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Select the input clock frequency.
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : HFRC_DIV64
Selects the HFRC / 64 as the input clock.
1 : HFRC
Selects the HFRC as the input clock.
2 : HFRC_DIV2
Selects the HFRC / 2 as the input clock.
3 : HFRC_DIV4
Selects the HFRC / 4 as the input clock.
4 : HFRC_DIV8
Selects the HFRC / 8 as the input clock.
5 : HFRC_DIV16
Selects the HFRC / 16 as the input clock.
6 : HFRC_DIV32
Selects the HFRC / 32 as the input clock.
End of enumeration elements list.
DIV3 : Enable divide by 3.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : DIS
Select divide by 1.
1 : EN
Select divide by 3.
End of enumeration elements list.
DIVEN : Enable clock division by TOTPER.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : DIS
Disable TOTPER division.
1 : EN
Enable TOTPER division.
End of enumeration elements list.
LOWPER : Clock low count minus 1.
bits : 16 - 39 (24 bit)
access : read-write
TOTPER : Clock total count minus 1.
bits : 24 - 55 (32 bit)
access : read-write
Command Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : This register is the I/O Command.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : POS_LENGTH
LSB bit position of the CMD LENGTH field.
8 : POS_OFFSET
LSB bit position of the CMD OFFSET field.
16 : POS_ADDRESS
LSB bit position of the I2C CMD ADDRESS field.
23 : POS_UPLNGTH
LSB bit position of the SPI CMD UPLNGTH field.
26 : POS_10BIT
LSB bit position of the I2C CMD 10-bit field.
27 : POS_LSB
LSB bit position of the CMD LSB-first field.
28 : POS_CONT
LSB bit position of the CMD CONTinue field.
29 : POS_OPER
LSB bit position of the CMD OPERation field.
255 : MSK_LENGTH
LSB bit mask of the CMD LENGTH field.
65280 : MSK_OFFSET
LSB bit mask of the CMD OFFSET field.
16711680 : MSK_ADDRESS
LSB bit mask of the I2C CMD ADDRESS field.
458752 : MSK_CHNL
LSB bit mask of the SPI CMD CHANNEL field.
125829120 : MSK_UPLNGTH
LSB bit mask of the SPI CMD UPLNGTH field.
67108864 : MSK_10BIT
LSB bit mask of the I2C CMD 10-bit field.
134217728 : MSK_LSB
LSB bit mask of the CMD LSB-first field.
268435456 : MSK_CONT
LSB bit mask of the CMD CONTinue field.
3758096384 : MSK_OPER
LSB bit mask of the CMD OPERation field.
End of enumeration elements list.
Command Repeat Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDRPT : These bits hold the Command repeat count.
bits : 0 - 4 (5 bit)
access : read-write
Status Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : This bit indicates if an error interrupt has occurred.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ERROR
An error has been indicated by the IOM.
End of enumeration elements list.
CMDACT : This bit indicates if the I/O Command is active.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : ACTIVE
An I/O command is active.
End of enumeration elements list.
IDLEST : This bit indicates if the I/O state machine is IDLE.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : IDLE
The I/O state machine is in the idle state.
End of enumeration elements list.
I/O Master Configuration
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFCSEL : This bit selects the I/O interface.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : I2C
Selects I2C interface for the I/O Master.
1 : SPI
Selects SPI interface for the I/O Master.
End of enumeration elements list.
SPOL : This bit selects SPI polarity.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : CLK_BASE_0
The base value of the clock is 0.
1 : CLK_BASE_1
The base value of the clock is 1.
End of enumeration elements list.
SPHA : This bit selects SPI phase.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : SAMPLE_LEADING_EDGE
Sample on the leading (first) clock edge.
1 : SAMPLE_TRAILING_EDGE
Sample on the trailing (second) clock edge.
End of enumeration elements list.
IFCEN : This bit enables the IO Master.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : DIS
Disable the IO Master.
1 : EN
Enable the IO Master.
End of enumeration elements list.
IO Master Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Write FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Read FIFO Overflow interrupt.
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the write length mismatch interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Write FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Read FIFO Overflow interrupt.
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the write length mismatch interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Write FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Read FIFO Overflow interrupt.
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the write length mismatch interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt.
bits : 10 - 20 (11 bit)
access : read-write
IO Master Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : This is the Command Complete interrupt.
bits : 0 - 0 (1 bit)
access : read-write
THR : This is the FIFO Threshold interrupt.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : This is the Write FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : This is the Read FIFO Overflow interrupt.
bits : 3 - 6 (4 bit)
access : read-write
NAK : This is the I2C NAK interrupt.
bits : 4 - 8 (5 bit)
access : read-write
WTLEN : This is the write length mismatch interrupt.
bits : 5 - 10 (6 bit)
access : read-write
IACC : This is the illegal FIFO access interrupt.
bits : 6 - 12 (7 bit)
access : read-write
ICMD : This is the illegal command interrupt.
bits : 7 - 14 (8 bit)
access : read-write
START : This is the START command interrupt.
bits : 8 - 16 (9 bit)
access : read-write
STOP : This is the STOP command interrupt.
bits : 9 - 18 (10 bit)
access : read-write
ARB : This is the arbitration loss interrupt.
bits : 10 - 20 (11 bit)
access : read-write
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