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IOSLAVE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x220 byte (0x0)
mem_usage : registers
protection :

Registers

FIFOPTR

FIFOCFG

FIFOTHR

FUPD

FIFOCTR

FIFOINC

CFG

PRENC

IOINTCTL

GENADD

INTEN

INTSTAT

INTCLR

INTSET

REGACCINTEN

REGACCINTSTAT

REGACCINTCLR

REGACCINTSET


FIFOPTR

Current FIFO Pointer
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOPTR FIFOPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOPTR FIFOSIZ

FIFOPTR : Current FIFO pointer.
bits : 0 - 7 (8 bit)
access : read-write

FIFOSIZ : The number of bytes currently in the hardware FIFO.
bits : 8 - 23 (16 bit)
access : read-write


FIFOCFG

FIFO Configuration
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOCFG FIFOCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOBASE FIFOMAX ROBASE

FIFOBASE : These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).
bits : 0 - 4 (5 bit)
access : read-write

FIFOMAX : These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.
bits : 8 - 21 (14 bit)
access : read-write

ROBASE : Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1)
bits : 24 - 53 (30 bit)
access : read-write


FIFOTHR

FIFO Threshold Configuration
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOTHR FIFOTHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOTHR

FIFOTHR : FIFO size interrupt threshold.
bits : 0 - 7 (8 bit)
access : read-write


FUPD

FIFO Update Status
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FUPD FUPD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOUPD IOREAD

FIFOUPD : This bit indicates that a FIFO update is underway.
bits : 0 - 0 (1 bit)
access : read-write

IOREAD : This bitfield indicates an IO read is active.
bits : 1 - 2 (2 bit)
access : read-write


FIFOCTR

Overall FIFO Counter
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOCTR FIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOCTR

FIFOCTR : Virtual FIFO byte count
bits : 0 - 9 (10 bit)
access : read-write


FIFOINC

Overall FIFO Counter Increment
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOINC FIFOINC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOINC

FIFOINC : Increment the Overall FIFO Counter by this value on a write
bits : 0 - 9 (10 bit)
access : read-write


CFG

I/O Slave Configuration
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFCSEL SPOL LSB STARTRD I2CADDR IFCEN

IFCSEL : This bit selects the I/O interface.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : I2C

Selects I2C interface for the IO Slave.

1 : SPI

Selects SPI interface for the IO Slave.

End of enumeration elements list.

SPOL : This bit selects SPI polarity.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : SPI_MODES_0_3

Polarity 0, handles SPI modes 0 and 3.

1 : SPI_MODES_1_2

Polarity 1, handles SPI modes 1 and 2.

End of enumeration elements list.

LSB : This bit selects the transfer bit ordering.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : MSB_FIRST

Data is assumed to be sent and received with MSB first.

1 : LSB_FIRST

Data is assumed to be sent and received with LSB first.

End of enumeration elements list.

STARTRD : This bit holds the cycle to initiate an I/O RAM read.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : LATE

Initiate I/O RAM read late in each transferred byte.

1 : EARLY

Initiate I/O RAM read early in each transferred byte.

End of enumeration elements list.

I2CADDR : 7-bit or 10-bit I2C device address.
bits : 8 - 27 (20 bit)
access : read-write

IFCEN : IOSLAVE interface enable.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : DIS

Disable the IOSLAVE

1 : EN

Enable the IOSLAVE

End of enumeration elements list.


PRENC

I/O Slave Interrupt Priority Encode
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRENC PRENC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRENC

PRENC : These bits hold the priority encode of the REGACC interrupts.
bits : 0 - 4 (5 bit)
access : read-write


IOINTCTL

I/O Interrupt Control
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOINTCTL IOINTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOINTEN IOINT IOINTCLR IOINTSET

IOINTEN : These bits setread the IOINT interrupt enables.
bits : 0 - 7 (8 bit)
access : read-write

IOINT : These bits read the IOINT interrupts.
bits : 8 - 23 (16 bit)
access : read-write

IOINTCLR : This bit clears all of the IOINT interrupts when written with a 1.
bits : 16 - 32 (17 bit)
access : read-write

IOINTSET : These bits set the IOINT interrupts when written with a 1.
bits : 24 - 55 (32 bit)
access : read-write


GENADD

General Address Data
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENADD GENADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GADATA

GADATA : The data supplied on the last General Address reference.
bits : 0 - 7 (8 bit)
access : read-write


INTEN

IO Slave Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSIZE FOVFL FUNDFL FRDERR GENAD IOINTW

FSIZE : FIFO Size interrupt.
bits : 0 - 0 (1 bit)
access : read-write

FOVFL : FIFO Overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

FRDERR : FIFO Read Error interrupt.
bits : 3 - 6 (4 bit)
access : read-write

GENAD : I2C General Address interrupt.
bits : 4 - 8 (5 bit)
access : read-write

IOINTW : I2C Interrupt Write interrupt.
bits : 5 - 10 (6 bit)
access : read-write


INTSTAT

IO Slave Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSIZE FOVFL FUNDFL FRDERR GENAD IOINTW

FSIZE : FIFO Size interrupt.
bits : 0 - 0 (1 bit)
access : read-write

FOVFL : FIFO Overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

FRDERR : FIFO Read Error interrupt.
bits : 3 - 6 (4 bit)
access : read-write

GENAD : I2C General Address interrupt.
bits : 4 - 8 (5 bit)
access : read-write

IOINTW : I2C Interrupt Write interrupt.
bits : 5 - 10 (6 bit)
access : read-write


INTCLR

IO Slave Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSIZE FOVFL FUNDFL FRDERR GENAD IOINTW

FSIZE : FIFO Size interrupt.
bits : 0 - 0 (1 bit)
access : read-write

FOVFL : FIFO Overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

FRDERR : FIFO Read Error interrupt.
bits : 3 - 6 (4 bit)
access : read-write

GENAD : I2C General Address interrupt.
bits : 4 - 8 (5 bit)
access : read-write

IOINTW : I2C Interrupt Write interrupt.
bits : 5 - 10 (6 bit)
access : read-write


INTSET

IO Slave Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSIZE FOVFL FUNDFL FRDERR GENAD IOINTW

FSIZE : FIFO Size interrupt.
bits : 0 - 0 (1 bit)
access : read-write

FOVFL : FIFO Overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : FIFO Underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

FRDERR : FIFO Read Error interrupt.
bits : 3 - 6 (4 bit)
access : read-write

GENAD : I2C General Address interrupt.
bits : 4 - 8 (5 bit)
access : read-write

IOINTW : I2C Interrupt Write interrupt.
bits : 5 - 10 (6 bit)
access : read-write


REGACCINTEN

Register Access Interrupts: Enable
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGACCINTEN REGACCINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGACC

REGACC : Register access interrupts.
bits : 0 - 31 (32 bit)
access : read-write


REGACCINTSTAT

Register Access Interrupts: Status
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGACCINTSTAT REGACCINTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGACC

REGACC : Register access interrupts.
bits : 0 - 31 (32 bit)
access : read-write


REGACCINTCLR

Register Access Interrupts: Clear
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGACCINTCLR REGACCINTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGACC

REGACC : Register access interrupts.
bits : 0 - 31 (32 bit)
access : read-write


REGACCINTSET

Register Access Interrupts: Set
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGACCINTSET REGACCINTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGACC

REGACC : Register access interrupts.
bits : 0 - 31 (32 bit)
access : read-write



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