Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x254 byte (0x0)
mem_usage : registers
protection :
Chip Information Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUAL : Device qualified.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PROTOTYPE
Prototype device.
1 : QUALIFIED
Fully qualified device.
End of enumeration elements list.
TEMP : Device temperature range.
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : COMMERCIAL
Commercial temperature range.
End of enumeration elements list.
PINS : Number of pins.
bits : 3 - 8 (6 bit)
access : read-write
Enumeration:
1 : 41PINS
41 package pins total.
End of enumeration elements list.
PKG : Device package type.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
2 : BGA
Ball grid array.
3 : CSP
Chip-scale package.
End of enumeration elements list.
MINORREV : Minor device revision number.
bits : 8 - 19 (12 bit)
access : read-write
MAJORREV : Major device revision number.
bits : 12 - 27 (16 bit)
access : read-write
RAM : Device RAM size.
bits : 16 - 35 (20 bit)
access : read-write
Enumeration:
0 : 32K
32K of available SRAM.
1 : 64K
64K of available SRAM.
End of enumeration elements list.
FLASH : Device flash size.
bits : 20 - 43 (24 bit)
access : read-write
Enumeration:
3 : 256K
256K of available flash.
4 : 512K
512K of available flash.
End of enumeration elements list.
CLASS : Device class.
bits : 24 - 55 (32 bit)
access : read-write
Enumeration:
1 : APOLLO
APOLLO
End of enumeration elements list.
Memory and Core Voltage Supply Source Select Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMBUCKEN : Enables and select the Memory Buck as the supply for the Flash and SRAM power domain.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable the Memory Buck as the supply for flash and SRAM.
End of enumeration elements list.
COREBUCKEN : Enables and Selects the Core Buck as the supply for the low-voltage power domain.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable the Core Buck for the low-voltage power domain.
End of enumeration elements list.
Memory and Core Voltage Supply Source Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMBUCKON : Indicate whether the Memory power domain is supplied from the LDO or the Buck.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LDO
Indicates the LDO is supplying the memory power domain.
1 : BUCK
Indicates the Buck is supplying the memory power domain.
End of enumeration elements list.
COREBUCKON : Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : LDO
Indicates the the LDO is supplying the Core low-voltage.
1 : BUCK
Indicates the the Buck is supplying the Core low-voltage.
End of enumeration elements list.
Powerdown an SRAM Bank in Deep Sleep mode
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BANK0 : Force SRAM Bank 0 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 0 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 0 deep sleep.
End of enumeration elements list.
BANK1 : Force SRAM Bank 1 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 1 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 1 deep sleep.
End of enumeration elements list.
BANK2 : Force SRAM Bank 2 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 2 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 2 deep sleep.
End of enumeration elements list.
BANK3 : Force SRAM Bank 3 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 3 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 3 deep sleep.
End of enumeration elements list.
BANK4 : Force SRAM Bank 4 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 4 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 4 deep sleep.
End of enumeration elements list.
BANK5 : Force SRAM Bank 5 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 5 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 5 deep sleep.
End of enumeration elements list.
BANK6 : Force SRAM Bank 6 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 6 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 6 deep sleep.
End of enumeration elements list.
BANK7 : Force SRAM Bank 7 to powerdown in deep sleep mode, causing the contents of the bank to be lost.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : NORMAL
SRAM Bank 7 normal operation.
1 : PWRDN_IN_DEEPSLEEP
SRAM Bank 7 deep sleep.
End of enumeration elements list.
Disables individual banks of the SRAM array
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BANK0 : Remove power from SRAM Bank 0 which will cause an access to its address space to generate a Hard Fault.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 0.
End of enumeration elements list.
BANK1 : Remove power from SRAM Bank 1 which will cause an access to its address space to generate a Hard Fault.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 1.
End of enumeration elements list.
BANK2 : Remove power from SRAM Bank 2 which will cause an access to its address space to generate a Hard Fault.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 2.
End of enumeration elements list.
BANK3 : Remove power from SRAM Bank 3 which will cause an access to its address space to generate a Hard Fault.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 3.
End of enumeration elements list.
BANK4 : Remove power from SRAM Bank 4 which will cause an access to its address space to generate a Hard Fault.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 4.
End of enumeration elements list.
BANK5 : Remove power from SRAM Bank 5 which will cause an access to its address space to generate a Hard Fault.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 5.
End of enumeration elements list.
BANK6 : Remove power from SRAM Bank 6 which will cause an access to its address space to generate a Hard Fault.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 6.
End of enumeration elements list.
BANK7 : Remove power from SRAM Bank 7 which will cause an access to its address space to generate a Hard Fault.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : DIS
Disable SRAM Bank 7.
End of enumeration elements list.
Disables individual banks of the Flash array
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BANK0 : Remove power from Flash Bank 0 which will cause an access to its address space to generate a Hard Fault.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : DIS
Disable Flash instance 0.
End of enumeration elements list.
BANK1 : Remove power from Flash Bank 1 which will cause an access to its address space to generate a Hard Fault.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : DIS
Disable Flash instance 1.
End of enumeration elements list.
ICODE bus address which was present when a bus fault occurred.
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write
DCODE bus address which was present when a bus fault occurred.
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write
System bus address which was present when a bus fault occurred.
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write
Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICODE : The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOFAULT
No ICODE fault has been detected.
1 : FAULT
ICODE fault detected.
End of enumeration elements list.
DCODE : DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : NOFAULT
No DCODE fault has been detected.
1 : FAULT
DCODE fault detected.
End of enumeration elements list.
SYS : SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : NOFAULT
No bus fault has been detected.
1 : FAULT
Bus fault detected.
End of enumeration elements list.
Enable the fault capture registers
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable fault capture.
1 : EN
Enable fault capture.
End of enumeration elements list.
TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable the TPIU.
1 : EN
Enable the TPIU.
End of enumeration elements list.
CLKSEL : This field selects the frequency of the ARM M4 TPIU port.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : LOW_PWR
Low power state.
1 : 6MHZ
Selects 6MHz frequency.
2 : 3MHZ
Selects 3MHz frequency.
3 : 1_5MHZ
Selects 1.5 MHz frequency.
End of enumeration elements list.
Unique Chip ID 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Unique chip ID 0.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : APOLLO
Apollo CHIPID0.
End of enumeration elements list.
Unique Chip ID 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Unique chip ID 1.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : APOLLO
Apollo CHIPID1.
End of enumeration elements list.
Chip Revision
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REVISION : Chip Revision Number.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : APOLLO
Apollo CHIPREV.
End of enumeration elements list.
Band Gap Enable
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGPEN : Bandgap Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Bandgap disable.
1 : EN
Bandgap enable.
End of enumeration elements list.
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