CACHECFG

NCR0START

NCR0END

NCR1START

NCR1END

CACHEMODE

FLASHCFG

DMON0

DMON1

DMON2

DMON3

IMON0

IMON1

IMON2

IMON3

CTRL

ENABLE : Enables the main flash cache controller logic and enables power to the cache RAMs. Instruction and Data caching need to be enabled independently using the ICACHE_ENABLE and DCACHE_ENABLE bits.
bits : 0 - 0 (1 bit)
access : read-write

LRU : Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM and is recommended.
bits : 1 - 2 (2 bit)
access : read-write

ENABLE_NC0 : Enable Non-cacheable region 0. See the NCR0 registers to set the region boundaries and size.
bits : 2 - 4 (3 bit)
access : read-write

ENABLE_NC1 : Enable Non-cacheable region 1. See the NCR1 registers to set the region boundaries and size.
bits : 3 - 6 (4 bit)
access : read-write

CONFIG : Sets the cache configuration. Only a single configuration of 0x5 is valid.
bits : 4 - 10 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SERIAL : Bitfield should always be programmed to 0.
bits : 7 - 14 (8 bit)
access : read-write

ICACHE_ENABLE : Enable Flash Instruction Caching. When set to 1, all instruction accesses to flash will be cached.
bits : 8 - 16 (9 bit)
access : read-write

DCACHE_ENABLE : Enable Flash Data Caching. When set to 1, all instruction accesses to flash will be cached.
bits : 9 - 18 (10 bit)
access : read-write

CACHE_CLKGATE : Enable clock gating of individual cache RAMs. This bit should be enabled for normal operation for lowest power consumption.
bits : 10 - 20 (11 bit)
access : read-write

CACHE_LS : Enable LS (light sleep) of cache RAMs. This should not be enabled for normal operation. When this bit is set, the cache's RAMS will be put into light sleep mode while inactive. NOTE: if the cache is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.
bits : 11 - 22 (12 bit)
access : read-write

DLY : Unused. Should be left at default value.
bits : 12 - 27 (16 bit)
access : read-write

SMDLY : Unused. Should be left at default value.
bits : 16 - 35 (20 bit)
access : read-write

DATA_CLKGATE : Enable clock gating of entire cache data array subsystem. This should be enabled for normal operation.
bits : 20 - 40 (21 bit)
access : read-write

ENABLE_MONITOR : Enable Cache Monitoring Stats. Only enable this for debug/performance analysis since it will consume additional power. See IMON/DMON registers for data.
bits : 24 - 48 (25 bit)
access : read-write

ADDR : Start address for non-cacheable region 0. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).
bits : 4 - 23 (20 bit)
access : read-write

ADDR : End address for non-cacheable region 0. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).
bits : 4 - 23 (20 bit)
access : read-write

ADDR : Start address for non-cacheable region 1. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).
bits : 4 - 23 (20 bit)
access : read-write

ADDR : End address for non-cacheable region 1. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused).
bits : 4 - 23 (20 bit)
access : read-write

THROTTLE1 : Disallow cache data RAM writes on tag RAM fill cycles. Value should be left at zero for optimal performance.
bits : 0 - 0 (1 bit)
access : read-write

THROTTLE2 : Disallow cache data RAM writes on tag RAM read cycles. Value should be left at zero for optimal performance.
bits : 1 - 2 (2 bit)
access : read-write

THROTTLE3 : Disallow cache data RAM writes on data RAM read cycles. Value should be left at zero for optimal performance.
bits : 2 - 4 (3 bit)
access : read-write

THROTTLE4 : Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should be left at zero for optimal performance.
bits : 3 - 6 (4 bit)
access : read-write

THROTTLE5 : Disallow Data RAM reads (from line hits) during lookup read ops. Value should be left at zero for optimal performance.
bits : 4 - 8 (5 bit)
access : read-write

THROTTLE6 : Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value should be left at zero for optimal performance.
bits : 5 - 10 (6 bit)
access : read-write

RD_WAIT : Sets read waitstates for flash accesses (in clock cycles). This should be left at the default value for normal flash operation.
bits : 0 - 2 (3 bit)
access : read-write

DACCESS_COUNT : Total accesses to data cache
bits : 0 - 31 (32 bit)
access : read-write

DLOOKUP_COUNT : Total tag lookups from data cache
bits : 0 - 31 (32 bit)
access : read-write

DHIT_COUNT : Cache hits from lookup operations
bits : 0 - 31 (32 bit)
access : read-write

DLINE_COUNT : Cache hits from line cache
bits : 0 - 31 (32 bit)
access : read-write

IACCESS_COUNT : Total accesses to Instruction cache
bits : 0 - 31 (32 bit)
access : read-write

ILOOKUP_COUNT : Total tag lookups from Instruction cache
bits : 0 - 31 (32 bit)
access : read-write

IHIT_COUNT : Cache hits from lookup operations
bits : 0 - 31 (32 bit)
access : read-write

ILINE_COUNT : Cache hits from line cache
bits : 0 - 31 (32 bit)
access : read-write

INVALIDATE : Writing a 1 to this bitfield invalidates the flash cache contents.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET_STAT : Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACHE_READY : Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation.
bits : 2 - 4 (3 bit)
access : read-write

FLASH0_SLM_STATUS : Flash Sleep Mode Status. When 1, flash instance 0 is asleep.
bits : 4 - 8 (5 bit)
access : read-write

FLASH0_SLM_DISABLE : Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.
bits : 5 - 10 (6 bit)
access : read-write

FLASH0_SLM_ENABLE : Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.
bits : 6 - 12 (7 bit)
access : read-write

FLASH1_SLM_STATUS : Flash Sleep Mode Status. When 1, flash instance 1 is asleep.
bits : 8 - 16 (9 bit)
access : read-write

FLASH1_SLM_DISABLE : Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.
bits : 9 - 18 (10 bit)
access : read-write

FLASH1_SLM_ENABLE : Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.
bits : 10 - 20 (11 bit)
access : read-write