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CLKGEN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection :

Registers

CALXT

CLKOUT

INTEN

INTSTAT

INTCLR

INTSET

CLKKEY

CCTRL

STATUS

HFADJ

CLOCKEN

CLOCKEN2

CLOCKEN3

UARTEN

CALRC

ACALCTR

OCTRL


CALXT

XT Oscillator Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALXT CALXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALXT

CALXT : XT Oscillator calibration value
bits : 0 - 10 (11 bit)
access : read-write


CLKOUT

CLKOUT Frequency Select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUT CLKOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKEN

CKSEL : CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high frequencies (such as from HFRC) are selected for CLKOUT.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : LFRC

LFRC

1 : XT_DIV2

XT / 2

2 : XT_DIV4

XT / 4

3 : XT_DIV8

XT / 8

4 : XT_DIV16

XT / 16

5 : XT_DIV32

XT / 32

16 : RTC_1Hz

1 Hz as selected in RTC

22 : XT_DIV2M

XT / 2^21

23 : XT

XT

24 : CG_100Hz

100 Hz as selected in CLKGEN

25 : HFRC

HFRC

26 : HFRC_DIV4

HFRC / 4

27 : HFRC_DIV8

HFRC / 8

28 : HFRC_DIV16

HFRC / 16

29 : HFRC_DIV64

HFRC / 64

30 : HFRC_DIV128

HFRC / 128

31 : HFRC_DIV256

HFRC / 256

32 : HFRC_DIV512

HFRC / 512

34 : FLASH_CLK

Flash Clock

35 : LFRC_DIV2

LFRC / 2

36 : LFRC_DIV32

LFRC / 32

37 : LFRC_DIV512

LFRC / 512

38 : LFRC_DIV32K

LFRC / 32768

39 : XT_DIV256

XT / 256

40 : XT_DIV8K

XT / 8192

41 : XT_DIV64K

XT / 2^16

42 : ULFRC_DIV16

Uncal LFRC / 16

43 : ULFRC_DIV128

Uncal LFRC / 128

44 : ULFRC_1Hz

Uncal LFRC / 1024

45 : ULFRC_DIV4K

Uncal LFRC / 4096

46 : ULFRC_DIV1M

Uncal LFRC / 2^20

47 : HFRC_DIV64K

HFRC / 2^16

48 : HFRC_DIV16M

HFRC / 2^24

49 : LFRC_DIV2M

LFRC / 2^20

50 : HFRCNE

HFRC (not autoenabled)

51 : HFRCNE_DIV8

HFRC / 8 (not autoenabled)

53 : XTNE

XT (not autoenabled)

54 : XTNE_DIV16

XT / 16 (not autoenabled)

55 : LFRCNE_DIV32

LFRC / 32 (not autoenabled)

57 : LFRCNE

LFRC (not autoenabled) - Default for undefined values

End of enumeration elements list.

CKEN : Enable the CLKOUT signal
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : DIS

Disable CLKOUT

1 : EN

Enable CLKOUT

End of enumeration elements list.


INTEN

CLKGEN Interrupt Register: Enable
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF ALM

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write

ALM : RTC Alarm interrupt
bits : 3 - 6 (4 bit)
access : read-write


INTSTAT

CLKGEN Interrupt Register: Status
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF ALM

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write

ALM : RTC Alarm interrupt
bits : 3 - 6 (4 bit)
access : read-write


INTCLR

CLKGEN Interrupt Register: Clear
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF ALM

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write

ALM : RTC Alarm interrupt
bits : 3 - 6 (4 bit)
access : read-write


INTSET

CLKGEN Interrupt Register: Set
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF ALM

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write

ALM : RTC Alarm interrupt
bits : 3 - 6 (4 bit)
access : read-write


CLKKEY

Key Register for Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKKEY CLKKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKKEY

CLKKEY : Key register value.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

71 : Key

Key

End of enumeration elements list.


CCTRL

HFRC Clock Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTRL CCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORESEL

CORESEL : Core Clock divisor
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HFRC

Core Clock is HFRC

1 : HFRC_DIV2

Core Clock is HFRC / 2

End of enumeration elements list.


STATUS

Clock Generator Status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OMODE OSCF

OMODE : Current RTC oscillator (1 => LFRC, 0 => XT)
bits : 0 - 0 (1 bit)
access : read-write

OSCF : XT Oscillator is enabled but not oscillating
bits : 1 - 2 (2 bit)
access : read-write


HFADJ

HFRC Adjustment
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFADJ HFADJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFADJEN HFADJCK HFXTADJ HFWARMUP HFADJ_GAIN

HFADJEN : HFRC adjustment control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable the HFRC adjustment

1 : EN

Enable the HFRC adjustment

End of enumeration elements list.

HFADJCK : Repeat period for HFRC adjustment
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0 : 4SEC

Autoadjust repeat period = 4 seconds

1 : 16SEC

Autoadjust repeat period = 16 seconds

2 : 32SEC

Autoadjust repeat period = 32 seconds

3 : 64SEC

Autoadjust repeat period = 64 seconds

4 : 128SEC

Autoadjust repeat period = 128 seconds

5 : 256SEC

Autoadjust repeat period = 256 seconds

6 : 512SEC

Autoadjust repeat period = 512 seconds

7 : 1024SEC

Autoadjust repeat period = 1024 seconds

End of enumeration elements list.

HFXTADJ : Target HFRC adjustment value.
bits : 8 - 27 (20 bit)
access : read-write

HFWARMUP : XT warmup period for HFRC adjustment
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : 1SEC

Autoadjust XT warmup period = 1-2 seconds

1 : 2SEC

Autoadjust XT warmup period = 2-4 seconds

End of enumeration elements list.

HFADJ_GAIN : Gain control for HFRC adjustment
bits : 21 - 44 (24 bit)
access : read-write

Enumeration:

0 : Gain_of_1

HF Adjust with Gain of 1

1 : Gain_of_1_in_2

HF Adjust with Gain of 0.5

2 : Gain_of_1_in_4

HF Adjust with Gain of 0.25

3 : Gain_of_1_in_8

HF Adjust with Gain of 0.125

4 : Gain_of_1_in_16

HF Adjust with Gain of 0.0625

5 : Gain_of_1_in_32

HF Adjust with Gain of 0.03125

End of enumeration elements list.


CLOCKEN

Clock Enable Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKEN CLOCKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKEN

CLOCKEN : Clock enable status
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

1 : ADC_CLKEN

Clock enable for the ADC.

2 : CTIMER_CLKEN

Clock enable for the CTIMER.

4 : CTIMER0A_CLKEN

Clock enable for the CTIMER0A.

8 : CTIMER0B_CLKEN

Clock enable for the CTIMER0B.

16 : CTIMER1A_CLKEN

Clock enable for the CTIMER1A.

32 : CTIMER1B_CLKEN

Clock enable for the CTIMER1B.

64 : CTIMER2A_CLKEN

Clock enable for the CTIMER2A.

128 : CTIMER2B_CLKEN

Clock enable for the CTIMER2B.

256 : CTIMER3A_CLKEN

Clock enable for the CTIMER3A.

512 : CTIMER3B_CLKEN

Clock enable for the CTIMER3B.

1024 : IOMSTR0_CLKEN

Clock enable for the IO Master 0.

2048 : IOMSTR1_CLKEN

Clock enable for the IO Master 1.

4096 : IOMSTR2_CLKEN

Clock enable for the IO Master 2.

8192 : IOMSTR3_CLKEN

Clock enable for the IO Master 3.

16384 : IOMSTR4_CLKEN

Clock enable for the IO Master 4.

32768 : IOMSTR5_CLKEN

Clock enable for the IO Master 5.

65536 : IOMSTRIFC0_CLKEN

Clock enable for the IO Master IFC0.

131072 : IOMSTRIFC1_CLKEN

Clock enable for the IO Master IFC1.

262144 : IOMSTRIFC2_CLKEN

Clock enable for the IO Master IFC2.

524288 : IOMSTRIFC3_CLKEN

Clock enable for the IO Master IFC3.

1048576 : IOMSTRIFC4_CLKEN

Clock enable for the IO Master IFC4.

2097152 : IOMSTRIFC5_CLKEN

Clock enable for the IO Master IFC5.

4194304 : IOSLAVE_CLKEN

Clock enable for the IO Slave.

8388608 : PDM_CLKEN

Clock enable for the PDM.

16777216 : PDMIFC_CLKEN

Clock enable for the PDM IFC.

33554432 : RSTGEN_CLKEN

Clock enable for the RSTGEN.

67108864 : SRAM_WIPE_CLKEN

Clock enable for the SRAM_WIPE.

134217728 : STIMER_CLKEN

Clock enable for the STIMER.

268435456 : STIMER_CNT_CLKEN

Clock enable for the STIMER_CNT.

536870912 : TPIU_CLKEN

Clock enable for the TPIU.

1073741824 : UART0_HCLK_CLKEN

Clock enable for the UART0_HCLK.

2147483648 : UART0HF_CLKEN

Clock enable for the UART0HF.

End of enumeration elements list.


CLOCKEN2

Clock Enable Status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKEN2 CLOCKEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKEN2

CLOCKEN2 : Clock enable status 2
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

1 : UART1_HCLK_CLKEN

Clock enable for the UART1_HCLK.

2 : UART1HF_CLKEN

Clock enable for the UART1HF.

4 : WDT_CLKEN

Clock enable for the WDT.

1073741824 : XT_32KHz_EN

Clock enable for the XT_32KHz.

2147483648 : FRCHFRC

Force HFRC On Status.

End of enumeration elements list.


CLOCKEN3

Clock Enable Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKEN3 CLOCKEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKEN3

CLOCKEN3 : Clock enable status 3
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

16777216 : periph_all_xtal_en

At least 1 peripherial is requesting for XTAL Clock

33554432 : periph_all_hfrc_en

At least 1 peripherial is requesting for HFRC Clock

67108864 : HFADJEN

HFRC Adjust Enable Status

134217728 : HFRC_en_out

HFRC is enabled during adjustment status

268435456 : RTC_SOURCE

Selects the RTC oscillator (0 => LFRC, 1 => XT)

536870912 : XTAL_EN

XT is enabled Status

1073741824 : HFRC_EN

HFRC is enabled Status

2147483648 : FLASHCLK_EN

Flash Clock is enabled Status

End of enumeration elements list.


UARTEN

UART Enable
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTEN UARTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0EN UART1EN

UART0EN : UART0 system clock control
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : DIS

Disable the UART0 system clock

1 : EN

Enable the UART0 system clock

2 : REDUCE_FREQ

Run UART_Hclk at the same frequency as UART_hfclk

3 : EN_POWER_SAV

Enable UART_hclk to reduce to UART_hfclk at low power mode

End of enumeration elements list.

UART1EN : UART1 system clock control
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable the UART1 system clock

1 : EN

Enable the UART1 system clock

2 : REDUCE_FREQ

Run UART_Hclk at the same frequency as UART_hfclk

3 : EN_POWER_SAV

Enable UART_hclk to reduce to UART_hfclk at low power mode

End of enumeration elements list.


CALRC

RC Oscillator Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALRC CALRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRC

CALRC : LFRC Oscillator calibration value
bits : 0 - 17 (18 bit)
access : read-write


ACALCTR

Autocalibration Counter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACALCTR ACALCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACALCTR

ACALCTR : Autocalibration Counter result.
bits : 0 - 23 (24 bit)
access : read-write


OCTRL

Oscillator Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCTRL OCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPXT STOPRC FOS OSEL ACAL

STOPXT : Stop the XT Oscillator to the RTC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : EN

Enable the XT Oscillator to drive the RTC

1 : STOP

Stop the XT Oscillator when driving the RTC

End of enumeration elements list.

STOPRC : Stop the LFRC Oscillator to the RTC
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : EN

Enable the LFRC Oscillator to drive the RTC

1 : STOP

Stop the LFRC Oscillator when driving the RTC

End of enumeration elements list.

FOS : Oscillator switch on failure function
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : DIS

Disable the oscillator switch on failure function

1 : EN

Enable the oscillator switch on failure function

End of enumeration elements list.

OSEL : Selects the RTC oscillator (1 => LFRC, 0 => XT)
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : RTC_XT

RTC uses the XT

1 : RTC_LFRC

RTC uses the LFRC

End of enumeration elements list.

ACAL : Autocalibration control
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable Autocalibration

2 : 1024SEC

Autocalibrate every 1024 seconds

3 : 512SEC

Autocalibrate every 512 seconds

6 : XTFREQ

Frequency measurement using XT

7 : EXTFREQ

Frequency measurement using external clock

End of enumeration elements list.



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