Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x310 byte (0x0)
mem_usage : registers
protection :
Counter/Timer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA0 : Counter/Timer A0.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB0 : Counter/Timer B0.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA1 : Counter/Timer A1.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB1 : Counter/Timer B1.
bits : 16 - 47 (32 bit)
access : read-write
Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Selects an appropriate clock source and divider to use for the System Timer clock.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : NOCLK
No clock enabled.
1 : HFRC_DIV16
3MHz from the HFRC clock divider.
2 : HFRC_DIV256
187.5KHz from the HFRC clock divider.
3 : XTAL_DIV1
32768Hz from the crystal oscillator.
4 : XTAL_DIV2
16384Hz from the crystal oscillator.
5 : XTAL_DIV32
1024Hz from the crystal oscillator.
6 : LFRC_DIV1
Approximately 1KHz from the LFRC oscillator (uncalibrated).
7 : CTIMER0A
Use CTIMER 0 section A as a prescaler for the clock source.
8 : CTIMER0B
Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.
End of enumeration elements list.
COMPARE_A_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare A disabled.
1 : ENABLE
Compare A enabled.
End of enumeration elements list.
COMPARE_B_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare B disabled.
1 : ENABLE
Compare B enabled.
End of enumeration elements list.
COMPARE_C_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare C disabled.
1 : ENABLE
Compare C enabled.
End of enumeration elements list.
COMPARE_D_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare D disabled.
1 : ENABLE
Compare D enabled.
End of enumeration elements list.
COMPARE_E_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare E disabled.
1 : ENABLE
Compare E enabled.
End of enumeration elements list.
COMPARE_F_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare F disabled.
1 : ENABLE
Compare F enabled.
End of enumeration elements list.
COMPARE_G_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare G disabled.
1 : ENABLE
Compare G enabled.
End of enumeration elements list.
COMPARE_H_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 15 - 30 (16 bit)
access : read-write
Enumeration:
0 : DISABLE
Compare H disabled.
1 : ENABLE
Compare H enabled.
End of enumeration elements list.
CLEAR : Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
0 : RUN
Let the COUNTER register run on its input clock.
1 : CLEAR
Stop the COUNTER register for loading.
End of enumeration elements list.
FREEZE : Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : THAW
Let the COUNTER register run on its input clock.
1 : FREEZE
Stop the COUNTER register for loading.
End of enumeration elements list.
System Timer Count Register (Real Time Counter)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write
Capture Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_A : Selects whether capture is enabled for the specified capture register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Capture function disabled.
1 : ENABLE
Capture function enabled.
End of enumeration elements list.
CAPTURE_B : Selects whether capture is enabled for the specified capture register.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Capture function disabled.
1 : ENABLE
Capture function enabled.
End of enumeration elements list.
CAPTURE_C : Selects whether capture is enabled for the specified capture register.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : DISABLE
Capture function disabled.
1 : ENABLE
Capture function enabled.
End of enumeration elements list.
CAPTURE_D : Selects whether capture is enabled for the specified capture register.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Capture function disabled.
1 : ENABLE
Capture function enabled.
End of enumeration elements list.
Compare Register A
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register B
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register C
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register D
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register E
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register F
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register G
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Compare Register H
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write
Counter/Timer A1 Compare Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A1 : Counter/Timer A1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A1 : Counter/Timer A1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B1 Compare Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B1 : Counter/Timer B1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B1 : Counter/Timer B1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA1EN : Counter/Timer A1 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A1 Disable.
1 : EN
Counter/Timer A1 Enable.
End of enumeration elements list.
TMRA1CLK : Counter/Timer A1 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream from MEM Buck.
End of enumeration elements list.
TMRA1FN : Counter/Timer A1 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A1, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA1IE0 : Counter/Timer A1 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A1 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer A1 to generate an interrupt based on COMPR0.
End of enumeration elements list.
TMRA1IE1 : Counter/Timer A1 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A1 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer A1 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRA1CLR : Counter/Timer A1 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A1 to run
1 : CLEAR
Holds counter/timer A1 at 0x0000.
End of enumeration elements list.
TMRA1POL : Counter/Timer A1 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA1 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA1 pin is the inverse of the timer output.
End of enumeration elements list.
TMRA1PE : Counter/Timer A1 Output Enable bit.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA1POL.
1 : EN
Enable counter/timer A1 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRB1EN : Counter/Timer B1 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B1 Disable.
1 : EN
Counter/Timer B1 Enable.
End of enumeration elements list.
TMRB1CLK : Counter/Timer B1 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream from CORE Buck.
End of enumeration elements list.
TMRB1FN : Counter/Timer B1 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B1, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB1IE0 : Counter/Timer B1 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B1 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer B1 to generate an interrupt based on COMPR0
End of enumeration elements list.
TMRB1IE1 : Counter/Timer B1 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B1 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer B1 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRB1CLR : Counter/Timer B1 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B1 to run
1 : CLEAR
Holds counter/timer B1 at 0x0000.
End of enumeration elements list.
TMRB1POL : Counter/Timer B1 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB1 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB1 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB1PE : Counter/Timer B1 Output Enable bit.
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB1POL.
1 : EN
Enable counter/timer B1 to generate a signal on TMRPINB.
End of enumeration elements list.
CTLINK1 : Counter/Timer A1/B1 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A1/B1 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A1/B1 timers into a single 32-bit timer.
End of enumeration elements list.
Capture Register A
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register B
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register C
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register D
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write
System Timer NVRAM_A Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write
System Timer NVRAM_B Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write
System Timer NVRAM_C Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write
Counter/Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA2 : Counter/Timer A2.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB2 : Counter/Timer B2.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write
CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 8 - 16 (9 bit)
access : read-write
CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 9 - 18 (10 bit)
access : read-write
CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 11 - 22 (12 bit)
access : read-write
CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 12 - 24 (13 bit)
access : read-write
CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 13 - 26 (14 bit)
access : read-write
CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 14 - 28 (15 bit)
access : read-write
CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 15 - 30 (16 bit)
access : read-write
Counter/Timer Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write
CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 8 - 16 (9 bit)
access : read-write
CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 9 - 18 (10 bit)
access : read-write
CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 11 - 22 (12 bit)
access : read-write
CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 12 - 24 (13 bit)
access : read-write
CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 13 - 26 (14 bit)
access : read-write
CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 14 - 28 (15 bit)
access : read-write
CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 15 - 30 (16 bit)
access : read-write
Counter/Timer Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write
CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 8 - 16 (9 bit)
access : read-write
CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 9 - 18 (10 bit)
access : read-write
CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 11 - 22 (12 bit)
access : read-write
CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 12 - 24 (13 bit)
access : read-write
CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 13 - 26 (14 bit)
access : read-write
CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 14 - 28 (15 bit)
access : read-write
CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 15 - 30 (16 bit)
access : read-write
Counter/Timer Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write
CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write
CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write
CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write
CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write
CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write
CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write
CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write
CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 8 - 16 (9 bit)
access : read-write
CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 9 - 18 (10 bit)
access : read-write
CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 11 - 22 (12 bit)
access : read-write
CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 12 - 24 (13 bit)
access : read-write
CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 13 - 26 (14 bit)
access : read-write
CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 14 - 28 (15 bit)
access : read-write
CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 15 - 30 (16 bit)
access : read-write
Counter/Timer A2 Compare Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A2 : Counter/Timer A2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A2 : Counter/Timer A2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B2 Compare Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B2 : Counter/Timer B2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B2 : Counter/Timer B2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA2EN : Counter/Timer A2 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A2 Disable.
1 : EN
Counter/Timer A2 Enable.
End of enumeration elements list.
TMRA2CLK : Counter/Timer A2 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream from CORE Buck.
End of enumeration elements list.
TMRA2FN : Counter/Timer A2 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A2, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA2IE0 : Counter/Timer A2 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A2 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer A2 to generate an interrupt based on COMPR0.
End of enumeration elements list.
TMRA2IE1 : Counter/Timer A2 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A2 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer A2 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRA2CLR : Counter/Timer A2 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A2 to run
1 : CLEAR
Holds counter/timer A2 at 0x0000.
End of enumeration elements list.
TMRA2POL : Counter/Timer A2 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA2 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA2 pin is the inverse of the timer output.
End of enumeration elements list.
TMRA2PE : Counter/Timer A2 Output Enable bit.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA2POL.
1 : EN
Enable counter/timer A2 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRB2EN : Counter/Timer B2 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B2 Disable.
1 : EN
Counter/Timer B2 Enable.
End of enumeration elements list.
TMRB2CLK : Counter/Timer B2 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream from MEM Buck.
End of enumeration elements list.
TMRB2FN : Counter/Timer B2 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B2, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB2IE0 : Counter/Timer B2 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B2 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer B2 to generate an interrupt based on COMPR0
End of enumeration elements list.
TMRB2IE1 : Counter/Timer B2 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B2 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer B2 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRB2CLR : Counter/Timer B2 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B2 to run
1 : CLEAR
Holds counter/timer B2 at 0x0000.
End of enumeration elements list.
TMRB2POL : Counter/Timer B2 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB2 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB2 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB2PE : Counter/Timer B2 Output Enable bit.
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB2POL.
1 : EN
Enable counter/timer B2 to generate a signal on TMRPINB.
End of enumeration elements list.
CTLINK2 : Counter/Timer A2/B2 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A2/B2 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A2/B2 timers into a single 32-bit timer.
End of enumeration elements list.
Counter/Timer Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTMRA3 : Counter/Timer A3.
bits : 0 - 15 (16 bit)
access : read-write
CTTMRB3 : Counter/Timer B3.
bits : 16 - 47 (32 bit)
access : read-write
STIMER Interrupt registers: Enable
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : OFLOW_INT
Overflow interrupt status bit was set.
End of enumeration elements list.
CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : CAPA_INT
CAPTURE A interrupt status bit was set.
End of enumeration elements list.
CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : CAPB_INT
CAPTURE B interrupt status bit was set.
End of enumeration elements list.
CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : CAPC_INT
CAPTURE C interrupt status bit was set.
End of enumeration elements list.
CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : CAPD_INT
Capture D interrupt status bit was set.
End of enumeration elements list.
STIMER Interrupt registers: Status
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : OFLOW_INT
Overflow interrupt status bit was set.
End of enumeration elements list.
CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : CAPA_INT
CAPTURE A interrupt status bit was set.
End of enumeration elements list.
CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : CAPB_INT
CAPTURE B interrupt status bit was set.
End of enumeration elements list.
CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : CAPC_INT
CAPTURE C interrupt status bit was set.
End of enumeration elements list.
CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : CAPD_INT
Capture D interrupt status bit was set.
End of enumeration elements list.
STIMER Interrupt registers: Clear
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : OFLOW_INT
Overflow interrupt status bit was set.
End of enumeration elements list.
CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : CAPA_INT
CAPTURE A interrupt status bit was set.
End of enumeration elements list.
CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : CAPB_INT
CAPTURE B interrupt status bit was set.
End of enumeration elements list.
CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : CAPC_INT
CAPTURE C interrupt status bit was set.
End of enumeration elements list.
CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : CAPD_INT
Capture D interrupt status bit was set.
End of enumeration elements list.
STIMER Interrupt registers: Set
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : COMPARED
COUNTER greater than or equal to COMPARE register.
End of enumeration elements list.
OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : OFLOW_INT
Overflow interrupt status bit was set.
End of enumeration elements list.
CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : CAPA_INT
CAPTURE A interrupt status bit was set.
End of enumeration elements list.
CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : CAPB_INT
CAPTURE B interrupt status bit was set.
End of enumeration elements list.
CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : CAPC_INT
CAPTURE C interrupt status bit was set.
End of enumeration elements list.
CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : CAPD_INT
Capture D interrupt status bit was set.
End of enumeration elements list.
Counter/Timer A3 Compare Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A3 : Counter/Timer A3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A3 : Counter/Timer A3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B3 Compare Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B3 : Counter/Timer B3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B3 : Counter/Timer B3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA3EN : Counter/Timer A3 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A3 Disable.
1 : EN
Counter/Timer A3 Enable.
End of enumeration elements list.
TMRA3CLK : Counter/Timer A3 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream from CORE Buck.
End of enumeration elements list.
TMRA3FN : Counter/Timer A3 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A3, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA3IE0 : Counter/Timer A3 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A3 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer A3 to generate an interrupt based on COMPR0.
End of enumeration elements list.
TMRA3IE1 : Counter/Timer A3 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A3 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer A3 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRA3CLR : Counter/Timer A3 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A3 to run
1 : CLEAR
Holds counter/timer A3 at 0x0000.
End of enumeration elements list.
TMRA3POL : Counter/Timer A3 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA3 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA3 pin is the inverse of the timer output.
End of enumeration elements list.
TMRA3PE : Counter/Timer A3 Output Enable bit.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA3POL.
1 : EN
Enable counter/timer A3 to generate a signal on TMRPINA.
End of enumeration elements list.
ADCEN : Special Timer A3 enable for ADC function.
bits : 15 - 30 (16 bit)
access : read-write
TMRB3EN : Counter/Timer B3 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B3 Disable.
1 : EN
Counter/Timer B3 Enable.
End of enumeration elements list.
TMRB3CLK : Counter/Timer B3 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKA
Clock source is buck converter stream from MEM Buck.
End of enumeration elements list.
TMRB3FN : Counter/Timer B3 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B3, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB3IE0 : Counter/Timer B3 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B3 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer B3 to generate an interrupt based on COMPR0
End of enumeration elements list.
TMRB3IE1 : Counter/Timer B3 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B3 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer B3 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRB3CLR : Counter/Timer B3 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B3 to run
1 : CLEAR
Holds counter/timer B3 at 0x0000.
End of enumeration elements list.
TMRB3POL : Counter/Timer B3 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB3 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB3 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB3PE : Counter/Timer B3 Output Enable bit.
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB3POL.
1 : EN
Enable counter/timer B3 to generate a signal on TMRPINB.
End of enumeration elements list.
CTLINK3 : Counter/Timer A3/B3 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A3/B3 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A3/B3 timers into a single 32-bit timer.
End of enumeration elements list.
Counter/Timer A0 Compare Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0A0 : Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1A0 : Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer B0 Compare Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPR0B0 : Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write
CMPR1B0 : Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write
Counter/Timer Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRA0EN : Counter/Timer A0 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A0 Disable.
1 : EN
Counter/Timer A0 Enable.
End of enumeration elements list.
TMRA0CLK : Counter/Timer A0 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINA.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK_DIV4
Clock source is HCLK / 4.
16 : BUCKA
Clock source is buck converter stream from MEM Buck.
End of enumeration elements list.
TMRA0FN : Counter/Timer A0 Function Select.
bits : 6 - 14 (9 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0A0, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRA0IE0 : Counter/Timer A0 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A0 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer A0 to generate an interrupt based on COMPR0.
End of enumeration elements list.
TMRA0IE1 : Counter/Timer A0 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer A0 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer A0 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRA0CLR : Counter/Timer A0 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer A0 to run
1 : CLEAR
Holds counter/timer A0 at 0x0000.
End of enumeration elements list.
TMRA0POL : Counter/Timer A0 output polarity.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINA0 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINA0 pin is the inverse of the timer output.
End of enumeration elements list.
TMRA0PE : Counter/Timer A0 Output Enable bit.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer A holds the TMRPINA signal at the value TMRA0POL.
1 : EN
Enable counter/timer A0 to generate a signal on TMRPINA.
End of enumeration elements list.
TMRB0EN : Counter/Timer B0 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B0 Disable.
1 : EN
Counter/Timer B0 Enable.
End of enumeration elements list.
TMRB0CLK : Counter/Timer B0 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write
Enumeration:
0 : TMRPIN
Clock source is TMRPINB.
1 : HFRC_DIV4
Clock source is HFRC / 4
2 : HFRC_DIV16
Clock source is HFRC / 16
3 : HFRC_DIV256
Clock source is HFRC / 256
4 : HFRC_DIV1024
Clock source is HFRC / 1024
5 : HFRC_DIV4K
Clock source is HFRC / 4096
6 : XT
Clock source is the XT (uncalibrated).
7 : XT_DIV2
Clock source is XT / 2
8 : XT_DIV16
Clock source is XT / 16
9 : XT_DIV256
Clock source is XT / 256
10 : LFRC_DIV2
Clock source is LFRC / 2
11 : LFRC_DIV32
Clock source is LFRC / 32
12 : LFRC_DIV1K
Clock source is LFRC / 1024
13 : LFRC
Clock source is LFRC
14 : RTC_100HZ
Clock source is 100 Hz from the current RTC oscillator.
15 : HCLK
Clock source is HCLK.
16 : BUCKB
Clock source is buck converter stream from CORE Buck.
End of enumeration elements list.
TMRB0FN : Counter/Timer B0 Function Select.
bits : 22 - 46 (25 bit)
access : read-write
Enumeration:
0 : SINGLECOUNT
Single count (output toggles and sticks). Count to CMPR0B0, stop.
1 : REPEATEDCOUNT
Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.
2 : PULSE_ONCE
Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop.
3 : PULSE_CONT
Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.
4 : CONTINUOUS
Continuous run (aka Free Run). Count continuously.
End of enumeration elements list.
TMRB0IE0 : Counter/Timer B0 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B0 from generating an interrupt based on COMPR0.
1 : EN
Enable counter/timer B0 to generate an interrupt based on COMPR0
End of enumeration elements list.
TMRB0IE1 : Counter/Timer B0 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Disable counter/timer B0 from generating an interrupt based on COMPR1.
1 : EN
Enable counter/timer B0 to generate an interrupt based on COMPR1.
End of enumeration elements list.
TMRB0CLR : Counter/Timer B0 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write
Enumeration:
0 : RUN
Allow counter/timer B0 to run
1 : CLEAR
Holds counter/timer B0 at 0x0000.
End of enumeration elements list.
TMRB0POL : Counter/Timer B0 output polarity.
bits : 28 - 56 (29 bit)
access : read-write
Enumeration:
0 : NORMAL
The polarity of the TMRPINB0 pin is the same as the timer output.
1 : INVERTED
The polarity of the TMRPINB0 pin is the inverse of the timer output.
End of enumeration elements list.
TMRB0PE : Counter/Timer B0 Output Enable bit.
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
0 : DIS
Counter/Timer B holds the TMRPINB signal at the value TMRB0POL.
1 : EN
Enable counter/timer B0 to generate a signal on TMRPINB.
End of enumeration elements list.
CTLINK0 : Counter/Timer A0/B0 Link bit.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : TWO_16BIT_TIMERS
Use A0/B0 timers as two independent 16-bit timers (default).
1 : 32BIT_TIMER
Link A0/B0 timers into a single 32-bit timer.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.