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MCUCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x34C byte (0x0)
mem_usage : registers
protection :

Registers

CHIP_INFO

VENDORID

BODPORCTRL

ADCPWRDLY

ADCCAL

ADCBATTLOAD

BUCKTRIM

XTALGENCTRL

DEBUGGER

BOOTLOADERLOW

SHADOWVALID

ICODEFAULTADDR

DCODEFAULTADDR

SYSFAULTADDR

FAULTSTATUS

FAULTCAPTUREEN

DBGR1

DBGR2

PMUENABLE

TPIUCTRL

CHIPID0

BUCK

BUCK3

CHIPID1

LDOREG1

LDOREG3

CHIPREV


CHIP_INFO

Chip Information Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_INFO CHIP_INFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM

PARTNUM : BCD part number.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

50331648 : APOLLO2

Apollo2 part number is 0x03XXXXXX.

16777216 : APOLLO

Apollo part number is 0x01XXXXXX.

4278190080 : PN_M

Mask for the PN field.

End of enumeration elements list.


VENDORID

Unique Vendor ID
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VENDORID VENDORID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Unique Vendor ID
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

1095582289 : AMBIQ

Ambiq Vendor ID

End of enumeration elements list.


BODPORCTRL

BOD and PDR control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODPORCTRL BODPORCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWDPDR PWDBOD PDREXTREFSEL BODEXTREFSEL

PWDPDR : PDR Power Down.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : PWR_DN

PDR power down

End of enumeration elements list.

PWDBOD : BOD Power Down.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : PWR_DN

BOD power down.

End of enumeration elements list.

PDREXTREFSEL : PDR External Reference Select.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : SELECT

PDR external reference select.

End of enumeration elements list.

BODEXTREFSEL : BOD External Reference Select.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : SELECT

BOD external reference select.

End of enumeration elements list.


ADCPWRDLY

ADC Power Up Delay Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCPWRDLY ADCPWRDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCPWR0 ADCPWR1

ADCPWR0 : ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.
bits : 0 - 7 (8 bit)
access : read-write

ADCPWR1 : ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.
bits : 8 - 23 (16 bit)
access : read-write


ADCCAL

ADC Calibration Control
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCCAL ADCCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALONPWRUP ADCCALIBRATED

CALONPWRUP : Run ADC Calibration on initial power up sequence
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable automatic calibration on initial power up

1 : EN

Enable automatic calibration on initial power up

End of enumeration elements list.

ADCCALIBRATED : Status for ADC Calibration
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : FALSE

ADC is not calibrated

1 : TRUE

ADC is calibrated

End of enumeration elements list.


ADCBATTLOAD

ADC Battery Load Enable
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCBATTLOAD ADCBATTLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BATTLOAD

BATTLOAD : Enable the ADC battery load resistor
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Battery load is disconnected

1 : EN

Battery load is enabled

End of enumeration elements list.


BUCKTRIM

Trim settings for Core and Mem buck modules
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCKTRIM BUCKTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMBUCKR1 COREBUCKR1_LO COREBUCKR1_HI RSVD2

MEMBUCKR1 : Trim values for BUCK regulator.
bits : 0 - 5 (6 bit)
access : read-write

COREBUCKR1_LO : Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI for the full trim value.
bits : 8 - 21 (14 bit)
access : read-write

COREBUCKR1_HI : Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO for the full trim value.
bits : 16 - 35 (20 bit)
access : read-write

RSVD2 : RESERVED.
bits : 24 - 53 (30 bit)
access : read-write


XTALGENCTRL

XTAL Oscillator General Control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTALGENCTRL XTALGENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACWARMUP XTALBIASTRIM XTALKSBIASTRIM

ACWARMUP : Auto-calibration delay control
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : 1SEC

Warmup period of 1-2 seconds

1 : 2SEC

Warmup period of 2-4 seconds

2 : 4SEC

Warmup period of 4-8 seconds

3 : 8SEC

Warmup period of 8-16 seconds

End of enumeration elements list.

XTALBIASTRIM : XTAL IBIAS trim
bits : 2 - 9 (8 bit)
access : read-write

XTALKSBIASTRIM : XTAL IBIAS Kick start trim . This trim value is used during the startup process to enable a faster lock and is applied when the kickstart signal is active.
bits : 8 - 21 (14 bit)
access : read-write


DEBUGGER

Debugger Access Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUGGER DEBUGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKOUT

LOCKOUT : Lockout of debugger (SWD).
bits : 0 - 0 (1 bit)
access : read-write


BOOTLOADERLOW

Determines whether the bootloader code is visible at address 0x00000000
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOTLOADERLOW BOOTLOADERLOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Determines whether the bootloader code is visible at address 0x00000000 or not.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : ADDR0

Bootloader code at 0x00000000.

End of enumeration elements list.


SHADOWVALID

Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOWVALID SHADOWVALID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALID BL_DSLEEP

VALID : Indicates whether the shadow registers contain valid data from the Flash Information Space.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : VALID

Flash information space contains valid data.

End of enumeration elements list.

BL_DSLEEP : Indicates whether the bootloader should sleep or deep sleep if no image loaded.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : DEEPSLEEP

Bootloader will go to deep sleep if no flash image loaded

End of enumeration elements list.


ICODEFAULTADDR

ICODE bus address which was present when a bus fault occurred.
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICODEFAULTADDR ICODEFAULTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write


DCODEFAULTADDR

DCODE bus address which was present when a bus fault occurred.
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCODEFAULTADDR DCODEFAULTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write


SYSFAULTADDR

System bus address which was present when a bus fault occurred.
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSFAULTADDR SYSFAULTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write


FAULTSTATUS

Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULTSTATUS FAULTSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICODE DCODE SYS

ICODE : The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOFAULT

No ICODE fault has been detected.

1 : FAULT

ICODE fault detected.

End of enumeration elements list.

DCODE : DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : NOFAULT

No DCODE fault has been detected.

1 : FAULT

DCODE fault detected.

End of enumeration elements list.

SYS : SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : NOFAULT

No bus fault has been detected.

1 : FAULT

Bus fault detected.

End of enumeration elements list.


FAULTCAPTUREEN

Enable the fault capture registers
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAULTCAPTUREEN FAULTCAPTUREEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable fault capture.

1 : EN

Enable fault capture.

End of enumeration elements list.


DBGR1

Read-only debug register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGR1 DBGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ONETO8

ONETO8 : Read-only register for communication validation
bits : 0 - 31 (32 bit)
access : read-write


DBGR2

Read-only debug register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGR2 DBGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COOLCODE

COOLCODE : Read-only register for communication validation
bits : 0 - 31 (32 bit)
access : read-write


PMUENABLE

Control bit to enable/disable the PMU
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMUENABLE PMUENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable MCU power management.

1 : EN

Enable MCU power management.

End of enumeration elements list.


TPIUCTRL

TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPIUCTRL TPIUCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE CLKSEL

ENABLE : TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable the TPIU.

1 : EN

Enable the TPIU.

End of enumeration elements list.

CLKSEL : This field selects the frequency of the ARM M4 TPIU port.
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

0 : LOW_PWR

Low power state.

1 : HFRC_DIV_2

Selects HFRC divided by 2 as the source TPIU clk

2 : HFRC_DIV_8

Selects HFRC divided by 8 as the source TPIU clk

3 : HFRC_DIV_16

Selects HFRC divided by 16 as the source TPIU clk

4 : HFRC_DIV_32

Selects HFRC divided by 32 as the source TPIU clk

End of enumeration elements list.


CHIPID0

Unique Chip ID 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPID0 CHIPID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Unique chip ID 0.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : APOLLO2

Apollo2 CHIPID0. The lower 32-bits of the 64-bit CHIPID value, which is unique for each part.

End of enumeration elements list.


BUCK

Analog Buck Control
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK BUCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKSWE BYPBUCKCORE COREBUCKPWD SLEEPBUCKANA MEMBUCKPWD BYPBUCKMEM COREBUCKRST MEMBUCKRST

BUCKSWE : Buck Register Software Override Enable. This will enable the override values for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to the control logic, instead of the normal power control module signal. Note - Must take care to have correct value for ALL the register bits when this SWE is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : OVERRIDE_DIS

BUCK Software Override Disable.

1 : OVERRIDE_EN

BUCK Software Override Enable.

End of enumeration elements list.

BYPBUCKCORE : Not used. Additional control of buck is available in the power control module
bits : 1 - 2 (2 bit)
access : read-write

COREBUCKPWD : Core buck power down override. 1=Powered Down 0=Enabled Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : EN

Core Buck enable.

End of enumeration elements list.

SLEEPBUCKANA : HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the hfrc_freq_clkgen internal bus (see internal Shelby-1473)
bits : 3 - 6 (4 bit)
access : read-write

MEMBUCKPWD : Memory buck power down override. 1=Powered Down 0=Enabled Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : EN

Memory Buck Enable.

End of enumeration elements list.

BYPBUCKMEM : Not used. Additional control of buck is available in the power control module
bits : 5 - 10 (6 bit)
access : read-write

COREBUCKRST : Reset control override for Core Buck 0=enabled, 1=reset Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module.
bits : 6 - 12 (7 bit)
access : read-write

MEMBUCKRST : Reset control override for Mem Buck 0=enabled, 1=reset Value is propagated only when the BUCKSWE bit is active, otherwise contrl is from the power control module.
bits : 7 - 14 (8 bit)
access : read-write


BUCK3

Buck control reg 3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK3 BUCK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COREBUCKHYSTTRIM COREBUCKZXTRIM COREBUCKBURSTEN COREBUCKLOTON MEMBUCKHYSTTRIM MEMBUCKZXTRIM MEMBUCKBURSTEN MEMBUCKLOTON

COREBUCKHYSTTRIM : Hysterisis trim for core buck
bits : 0 - 1 (2 bit)
access : read-write

COREBUCKZXTRIM : Core buck zero crossing trim value
bits : 2 - 7 (6 bit)
access : read-write

COREBUCKBURSTEN : Core Buck burst enable. 0=disabled, 1=enabled
bits : 6 - 12 (7 bit)
access : read-write

COREBUCKLOTON : Core Buck low TON trim value
bits : 7 - 17 (11 bit)
access : read-write

MEMBUCKHYSTTRIM : Hysterisis trim for mem buck
bits : 11 - 23 (13 bit)
access : read-write

MEMBUCKZXTRIM : Memory buck zero crossing trim value
bits : 13 - 29 (17 bit)
access : read-write

MEMBUCKBURSTEN : MEM Buck burst enable 0=disable, 0=disabled, 1=enable.
bits : 17 - 34 (18 bit)
access : read-write

MEMBUCKLOTON : MEM Buck low TON trim value
bits : 18 - 39 (22 bit)
access : read-write


CHIPID1

Unique Chip ID 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPID1 CHIPID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Unique chip ID 1.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : APOLLO2

Apollo2 CHIPID1. The upper 32-bits of the 64-bit CHIPID value, which is unique for each part.

End of enumeration elements list.


LDOREG1

Analog LDO Reg 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDOREG1 LDOREG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMCORELDOR1 TRIMCORELDOR3 CORELDOLPTRIM CORELDOIBSTRM

TRIMCORELDOR1 : CORE LDO Active mode ouput trim (R1).
bits : 0 - 9 (10 bit)
access : read-write

TRIMCORELDOR3 : CORE LDO tempco trim (R3).
bits : 10 - 23 (14 bit)
access : read-write

CORELDOLPTRIM : CORE LDO Low Power Trim
bits : 14 - 33 (20 bit)
access : read-write

CORELDOIBSTRM : CORE LDO IBIAS Trim
bits : 20 - 40 (21 bit)
access : read-write


LDOREG3

LDO Control Register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDOREG3 LDOREG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMLDOLPTRIM MEMLDOLPALTTRIM TRIMMEMLDOR1

MEMLDOLPTRIM : MEM LDO TRIM for low power mode with ADC inactive
bits : 0 - 5 (6 bit)
access : read-write

MEMLDOLPALTTRIM : MEM LDO TRIM for low power mode with ADC active
bits : 6 - 17 (12 bit)
access : read-write

TRIMMEMLDOR1 : MEM LDO active mode trim (R1).
bits : 12 - 29 (18 bit)
access : read-write


CHIPREV

Chip Revision
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPREV CHIPREV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVMIN REVMAJ

REVMIN : Minor Revision ID.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : REV0

Apollo2 minor revision value. Succeeding minor revisions will increment from this value.

2 : REV2

Apollo2 minor revision value.

End of enumeration elements list.

REVMAJ : Major Revision ID.
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

2 : B

Apollo2 revision B

1 : A

Apollo2 revision A

End of enumeration elements list.



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