Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :
PDM Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMCORE : Data Streaming Control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable Data Streaming.
0 : DIS
Disable Data Streaming.
End of enumeration elements list.
SOFTMUTE : Soft mute control.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable Soft Mute.
0 : DIS
Disable Soft Mute.
End of enumeration elements list.
CYCLES : Number of clocks during gain-setting changes.
bits : 2 - 6 (5 bit)
access : read-write
HPCUTOFF : High pass filter coefficients.
bits : 5 - 13 (9 bit)
access : read-write
ADCHPD : High pass filter disable.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : EN
Enable high pass filter.
1 : DIS
Disable high pass filter.
End of enumeration elements list.
SINCRATE : SINC decimation rate.
bits : 10 - 26 (17 bit)
access : read-write
MCLKDIV : PDM_CLK frequency divisor.
bits : 17 - 35 (19 bit)
access : read-write
Enumeration:
3 : MCKDIV4
Divide input clock by 4
2 : MCKDIV3
Divide input clock by 3
1 : MCKDIV2
Divide input clock by 2
0 : MCKDIV1
Divide input clock by 1
End of enumeration elements list.
PGALEFT : Left channel PGA gain.
bits : 23 - 49 (27 bit)
access : read-write
Enumeration:
15 : M15DB
-1.5 db gain.
14 : M300DB
-3.0 db gain.
13 : M45DB
-4.5 db gain.
12 : M60DB
-6.0 db gain.
11 : M75DB
-7.5 db gain.
10 : M90DB
-9.0 db gain.
9 : M105DB
-10.5 db gain.
8 : M120DB
-12.0 db gain.
7 : P105DB
10.5 db gain.
6 : P90DB
9.0 db gain.
5 : P75DB
7.5 db gain.
4 : P60DB
6.0 db gain.
3 : P45DB
4.5 db gain.
2 : P30DB
3.0 db gain.
1 : P15DB
1.5 db gain.
0 : 0DB
0.0 db gain.
End of enumeration elements list.
PGARIGHT : Right channel PGA gain.
bits : 27 - 57 (31 bit)
access : read-write
Enumeration:
15 : M15DB
-1.5 db gain.
14 : M300DB
-3.0 db gain.
13 : M45DB
-4.5 db gain.
12 : M60DB
-6.0 db gain.
11 : M75DB
-7.5 db gain.
10 : M90DB
-9.0 db gain.
9 : M105DB
-10.5 db gain.
8 : M120DB
-12.0 db gain.
7 : P105DB
10.5 db gain.
6 : P90DB
9.0 db gain.
5 : P75DB
7.5 db gain.
4 : P60DB
6.0 db gain.
3 : P45DB
4.5 db gain.
2 : P30DB
3.0 db gain.
1 : P15DB
1.5 db gain.
0 : 0DB
0.0 db gain.
End of enumeration elements list.
LRSWAP : Left/right channel swap.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Swap left and right channels (FIFO Read RIGHT_LEFT).
0 : NOSWAP
No channel swapping (IFO Read LEFT_RIGHT).
End of enumeration elements list.
FIFO Flush
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOFLUSH : FIFO FLUSH.
bits : 0 - 0 (1 bit)
access : read-write
FIFO Threshold
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOTHR : FIFO interrupt threshold.
bits : 0 - 7 (8 bit)
access : read-write
IO Master Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write
OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write
UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
IO Master Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write
OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write
UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
IO Master Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write
OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write
UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
IO Master Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write
OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write
UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write
Voice Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSET : Set PCM channels.
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
0 : DIS
Channel disabled.
1 : LEFT
Mono left channel.
2 : RIGHT
Mono right channel.
3 : STEREO
Stereo channels.
End of enumeration elements list.
PCMPACK : PCM data packing enable.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : DIS
Disable PCM packing.
1 : EN
Enable PCM packing.
End of enumeration elements list.
SELAP : Select PDM input clock source.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
1 : I2S
Clock source from I2S BCLK.
0 : INTERNAL
Clock source from internal clock generator.
End of enumeration elements list.
DMICKDEL : PDM clock sampling delay.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : 0CYC
No delay.
1 : 1CYC
1 cycle delay.
End of enumeration elements list.
BCLKINV : I2S BCLK input inversion.
bits : 19 - 38 (20 bit)
access : read-write
Enumeration:
0 : INV
BCLK inverted.
1 : NORM
BCLK not inverted.
End of enumeration elements list.
I2SMODE : I2S interface enable.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : DIS
Disable I2S interface.
1 : EN
Enable I2S interface.
End of enumeration elements list.
PDMCLK : Enable the serial clock.
bits : 26 - 52 (27 bit)
access : read-write
Enumeration:
0 : DIS
Disable serial clock.
1 : EN
Enable serial clock.
End of enumeration elements list.
PDMCLKSEL : Select the PDM input clock.
bits : 27 - 56 (30 bit)
access : read-write
Enumeration:
0 : DISABLE
Static value.
1 : 12MHz
PDM clock is 12 MHz.
2 : 6MHz
PDM clock is 6 MHz.
3 : 3MHz
PDM clock is 3 MHz.
4 : 1_5MHz
PDM clock is 1.5 MHz.
5 : 750KHz
PDM clock is 750 KHz.
6 : 375KHz
PDM clock is 375 KHz.
7 : 187KHz
PDM clock is 187.5 KHz.
End of enumeration elements list.
RSTB : Reset the IP core.
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
0 : RESET
Reset the core.
1 : NORM
Enable the core.
End of enumeration elements list.
IOCLKEN : Enable the IO clock.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : DIS
Disable FIFO read.
1 : EN
Enable FIFO read.
End of enumeration elements list.
Voice Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOCNT : Valid 32-bit entries currently in the FIFO.
bits : 0 - 8 (9 bit)
access : read-write
FIFO Read
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOREAD : FIFO read data.
bits : 0 - 31 (32 bit)
access : read-write
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