\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
Memory and Core Voltage Supply Source Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMBUCKEN : Enables and select the Memory Buck as the supply for the Flash and SRAM power domain.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable the Memory Buck as the supply for flash and SRAM.
End of enumeration elements list.
COREBUCKEN : Enables and Selects the Core Buck as the supply for the low-voltage power domain.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable the Core Buck for the low-voltage power domain.
End of enumeration elements list.
SWITCH_LDO_IN_SLEEP : Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in DEEP SLEEP. If all the devices are off then this does not matter and LDO (low power mode) is used
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Automatically switch from CORE BUCK to CORE LDO when CPU is in DEEP SLEEP
End of enumeration elements list.
Disables individual banks of the MEMORY array
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMEN : Enables power for selected SRAM banks (else an access to its address space to generate a Hard Fault).
bits : 0 - 10 (11 bit)
access : read-write
Enumeration:
0 : NONE
All banks disabled
1 : GROUP0_SRAM0
0KB-8KB SRAM
2 : GROUP0_SRAM1
8KB-16KB SRAM
4 : GROUP0_SRAM2
16KB-24KB SRAM
8 : GROUP0_SRAM3
24KB-32KB SRAM
16 : GROUP1
32KB-64KB SRAMs
32 : GROUP2
64KB-96KB SRAMs
64 : GROUP3
96KB-128KB SRAMs
128 : GROUP4
128KB-160KB SRAMs
256 : GROUP5
160KB-192KB SRAMs
512 : GROUP6
192KB-224KB SRAMs
1024 : GROUP7
224KB-256KB SRAMs
3 : SRAM16K
ENABLE lower 16KB
15 : SRAM32K
ENABLE lower 32KB
31 : SRAM64K
ENABLE lower 64KB
127 : SRAM128K
ENABLE lower 128KB
2047 : SRAM256K
ENABLE lower 256KB
End of enumeration elements list.
FLASH0 : Enable FLASH 0
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : EN
Enable FLASH 0
0 : DIS
Disables FLASH 0
End of enumeration elements list.
FLASH1 : Enable FLASH1
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : EN
Enable FLASH1
0 : DIS
Disables FLASH1
End of enumeration elements list.
CACHEB0 : Enable CACHE BANK 0
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
1 : EN
Enable CACHE BANK 0
0 : DIS
Disable CACHE BANK 0
End of enumeration elements list.
CACHEB2 : Enable CACHE BANK 2
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Enable CACHE BANK 2
0 : DIS
Disable CACHE BANK 2
End of enumeration elements list.
POWER ON Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDA : This bit is 1 if power is supplied to power domain A, which supplies IOS and UART0,1.
bits : 1 - 2 (2 bit)
access : read-write
PDB : This bit is 1 if power is supplied to power domain B, which supplies IOM0-2.
bits : 2 - 4 (3 bit)
access : read-write
PDC : This bit is 1 if power is supplied to power domain C, which supplies IOM3-5.
bits : 3 - 6 (4 bit)
access : read-write
PD_PDM : This bit is 1 if power is supplied to domain PD_PDM
bits : 4 - 8 (5 bit)
access : read-write
PD_FLAM0 : This bit is 1 if power is supplied to domain PD_FLAM0
bits : 5 - 10 (6 bit)
access : read-write
PD_FLAM1 : This bit is 1 if power is supplied to domain PD_FLAM1
bits : 6 - 12 (7 bit)
access : read-write
PDADC : This bit is 1 if power is supplied to domain PD_ADC
bits : 7 - 14 (8 bit)
access : read-write
PD_GRP0_SRAM0 : This bit is 1 if power is supplied to SRAM domain SRAM0_0
bits : 8 - 16 (9 bit)
access : read-write
PD_GRP0_SRAM1 : This bit is 1 if power is supplied to SRAM domain SRAM0_1
bits : 9 - 18 (10 bit)
access : read-write
PD_GRP0_SRAM2 : This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2
bits : 10 - 20 (11 bit)
access : read-write
PD_GRP0_SRAM3 : This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3
bits : 11 - 22 (12 bit)
access : read-write
PD_GRP1_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP1
bits : 12 - 24 (13 bit)
access : read-write
PD_GRP2_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP2
bits : 13 - 26 (14 bit)
access : read-write
PD_GRP3_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP3
bits : 14 - 28 (15 bit)
access : read-write
PD_GRP4_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP4
bits : 15 - 30 (16 bit)
access : read-write
PD_GRP5_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP5
bits : 16 - 32 (17 bit)
access : read-write
PD_GRP6_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP6
bits : 17 - 34 (18 bit)
access : read-write
PD_GRP7_SRAM : This bit is 1 if power is supplied to SRAM domain PD_GRP7
bits : 18 - 36 (19 bit)
access : read-write
PD_CACHEB0 : This bit is 1 if power is supplied to CACHE BANK 0
bits : 19 - 38 (20 bit)
access : read-write
PD_CACHEB2 : This bit is 1 if power is supplied to CACHE BANK 2
bits : 21 - 42 (22 bit)
access : read-write
SRAM Control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_LIGHT_SLEEP : Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will be put into light sleep mode while inactive. NOTE: if the SRAM is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable LIGHT SLEEP for SRAMs
0 : DIS
Disables LIGHT SLEEP for SRAMs
End of enumeration elements list.
SRAM_CLKGATE : Enables individual per-RAM clock gating in the SRAM block. This bit should be enabled for lowest power operation.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable Individual SRAM Clock Gating
0 : DIS
Disables Individual SRAM Clock Gating
End of enumeration elements list.
SRAM_MASTER_CLKGATE : Enables top-level clock gating in the SRAM block. This bit should be enabled for lowest power operation.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Enable Master SRAM Clock Gate
0 : DIS
Disables Master SRAM Clock Gating
End of enumeration elements list.
Power Status Register for ADC Block
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_PWD : This bit indicates that the ADC is powered down
bits : 0 - 0 (1 bit)
access : read-write
ADC_BGT_PWD : This bit indicates that the ADC Band Gap is powered down
bits : 1 - 2 (2 bit)
access : read-write
ADC_VPTAT_PWD : This bit indicates that the ADC temperature sensor input buffer is powered down
bits : 2 - 4 (3 bit)
access : read-write
ADC_VBAT_PWD : This bit indicates that the ADC VBAT resistor divider is powered down
bits : 3 - 6 (4 bit)
access : read-write
ADC_REFKEEP_PWD : This bit indicates that the ADC REFKEEP is powered down
bits : 4 - 8 (5 bit)
access : read-write
ADC_REFBUF_PWD : This bit indicates that the ADC REFBUF is powered down
bits : 5 - 10 (6 bit)
access : read-write
Power Optimization Control Bits
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS_LDOLPMODE_TIMERS : Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep even when the ctimers or stimers are running
bits : 2 - 4 (3 bit)
access : read-write
Power Status Register for MCU supplies and peripherals
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMBUCKON : Indicate whether the Memory power domain is supplied from the LDO or the Buck.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LDO
Indicates the LDO is supplying the memory power domain.
1 : BUCK
Indicates the Buck is supplying the memory power domain.
End of enumeration elements list.
COREBUCKON : Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : LDO
Indicates the the LDO is supplying the Core low-voltage.
1 : BUCK
Indicates the the Buck is supplying the Core low-voltage.
End of enumeration elements list.
DEVICE ENABLES for SHELBY
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO_SLAVE : Enable IO SLAVE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable IO SLAVE
0 : DIS
Disables IO SLAVE
End of enumeration elements list.
IO_MASTER0 : Enable IO MASTER 0
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 0
0 : DIS
Disables IO MASTER 0
End of enumeration elements list.
IO_MASTER1 : Enable IO MASTER 1
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 1
0 : DIS
Disables IO MASTER 1
End of enumeration elements list.
IO_MASTER2 : Enable IO MASTER 2
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 2
0 : DIS
Disables IO MASTER 2
End of enumeration elements list.
IO_MASTER3 : Enable IO MASTER 3
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 3
0 : DIS
Disables IO MASTER 3
End of enumeration elements list.
IO_MASTER4 : Enable IO MASTER 4
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 4
0 : DIS
Disables IO MASTER 4
End of enumeration elements list.
IO_MASTER5 : Enable IO MASTER 5
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : EN
Enable IO MASTER 5
0 : DIS
Disables IO MASTER 5
End of enumeration elements list.
PWRUART0 : Enable UART 0
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : EN
Enable UART 0
0 : DIS
Disables UART 0
End of enumeration elements list.
PWRUART1 : Enable UART 1
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : EN
Enable UART 1
0 : DIS
Disables UART 1
End of enumeration elements list.
PWRADC : Enable ADC Digital Block
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : EN
Enable ADC
0 : DIS
Disables ADC
End of enumeration elements list.
PWRPDM : Enable PDM Digital Block
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : EN
Enable PDM
0 : DIS
Disables PDM
End of enumeration elements list.
Powerdown an SRAM Banks in Deep Sleep mode
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMSLEEPPOWERDOWN : Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.
bits : 0 - 10 (11 bit)
access : read-write
Enumeration:
0 : NONE
All banks retained
1 : GROUP0_SRAM0
0KB-8KB SRAM
2 : GROUP0_SRAM1
8KB-16KB SRAM
4 : GROUP0_SRAM2
16KB-24KB SRAM
8 : GROUP0_SRAM3
24KB-32KB SRAM
16 : GROUP1
32KB-64KB SRAMs
32 : GROUP2
64KB-96KB SRAMs
64 : GROUP3
96KB-128KB SRAMs
128 : GROUP4
128KB-160KB SRAMs
256 : GROUP5
160KB-192KB SRAMs
512 : GROUP6
192KB-224KB SRAMs
1024 : GROUP7
224KB-256KB SRAMs
3 : SRAM16K
Do not Retain lower 16KB
15 : SRAM32K
Do not Retain lower 32KB
31 : SRAM64K
Do not Retain lower 64KB
127 : SRAM128K
Do not Retain lower 128KB
2046 : ALLBUTLOWER8K
All banks but lower 8k powered down.
2044 : ALLBUTLOWER16K
All banks but lower 16k powered down.
2040 : ALLBUTLOWER24K
All banks but lower 24k powered down.
2032 : ALLBUTLOWER32K
All banks but lower 32k powered down.
2016 : ALLBUTLOWER64K
All banks but lower 64k powered down.
1920 : ALLBUTLOWER128K
All banks but lower 128k powered down.
2047 : ALL
All banks powered down.
End of enumeration elements list.
CACHE_PWD_SLP : Enable CACHE BANKS to power down in deep sleep
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
CACHE BANKS POWER DOWN in CORE SLEEP
0 : DIS
CACHE BANKS STAYS in Retention in CORE SLEEP
End of enumeration elements list.
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