\n
address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :
Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODHREN : Brown out high (2.1v) reset enable.
bits : 0 - 0 (1 bit)
access : read-write
WDREN : Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset.
bits : 1 - 2 (2 bit)
access : read-write
Clear the status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRSTAT : Writing a 1 to this bit clears all bits in the RST_STAT.
bits : 0 - 0 (1 bit)
access : read-write
TPIU reset
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPIURST : Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.
bits : 0 - 0 (1 bit)
access : read-write
Reset Interrupt register: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write
Reset Interrupt register: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write
Reset Interrupt register: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write
Reset Interrupt register: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write
Software POI Reset
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWPOIKEY : 0x1B generates a software POI reset.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
27 : KEYVALUE
Writing 0x1B key value generates a software POI reset.
End of enumeration elements list.
Software POR Reset
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWPORKEY : 0xD4 generates a software POR reset.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
212 : KEYVALUE
Writing 0xD4 key value generates a software POR reset.
End of enumeration elements list.
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXRSTAT : Reset was initiated by an External Reset.
bits : 0 - 0 (1 bit)
access : read-write
PORSTAT : Reset was initiated by a Power-On Reset.
bits : 1 - 2 (2 bit)
access : read-write
BORSTAT : Reset was initiated by a Brown-Out Reset.
bits : 2 - 4 (3 bit)
access : read-write
SWRSTAT : Reset was a initiated by SW POR or AIRCR Reset.
bits : 3 - 6 (4 bit)
access : read-write
POIRSTAT : Reset was a initiated by Software POI Reset.
bits : 4 - 8 (5 bit)
access : read-write
DBGRSTAT : Reset was a initiated by Debugger Reset.
bits : 5 - 10 (6 bit)
access : read-write
WDRSTAT : Reset was initiated by a Watchdog Timer Reset.
bits : 6 - 12 (7 bit)
access : read-write
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