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RSTGEN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

CLRSTAT

TPIU_RST

INTEN

INTSTAT

INTCLR

INTSET

SWPOI

SWPOR

STAT


CFG

Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODHREN WDREN

BODHREN : Brown out high (2.1v) reset enable.
bits : 0 - 0 (1 bit)
access : read-write

WDREN : Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset.
bits : 1 - 2 (2 bit)
access : read-write


CLRSTAT

Clear the status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLRSTAT CLRSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRSTAT

CLRSTAT : Writing a 1 to this bit clears all bits in the RST_STAT.
bits : 0 - 0 (1 bit)
access : read-write


TPIU_RST

TPIU reset
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPIU_RST TPIU_RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPIURST

TPIURST : Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.
bits : 0 - 0 (1 bit)
access : read-write


INTEN

Reset Interrupt register: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODH

BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write


INTSTAT

Reset Interrupt register: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODH

BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write


INTCLR

Reset Interrupt register: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODH

BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write


INTSET

Reset Interrupt register: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODH

BODH : Enables an interrupt that triggers when VCC is below BODH level.
bits : 0 - 0 (1 bit)
access : read-write


SWPOI

Software POI Reset
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWPOI SWPOI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWPOIKEY

SWPOIKEY : 0x1B generates a software POI reset.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

27 : KEYVALUE

Writing 0x1B key value generates a software POI reset.

End of enumeration elements list.


SWPOR

Software POR Reset
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWPOR SWPOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWPORKEY

SWPORKEY : 0xD4 generates a software POR reset.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

212 : KEYVALUE

Writing 0xD4 key value generates a software POR reset.

End of enumeration elements list.


STAT

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXRSTAT PORSTAT BORSTAT SWRSTAT POIRSTAT DBGRSTAT WDRSTAT

EXRSTAT : Reset was initiated by an External Reset.
bits : 0 - 0 (1 bit)
access : read-write

PORSTAT : Reset was initiated by a Power-On Reset.
bits : 1 - 2 (2 bit)
access : read-write

BORSTAT : Reset was initiated by a Brown-Out Reset.
bits : 2 - 4 (3 bit)
access : read-write

SWRSTAT : Reset was a initiated by SW POR or AIRCR Reset.
bits : 3 - 6 (4 bit)
access : read-write

POIRSTAT : Reset was a initiated by Software POI Reset.
bits : 4 - 8 (5 bit)
access : read-write

DBGRSTAT : Reset was a initiated by Debugger Reset.
bits : 5 - 10 (6 bit)
access : read-write

WDRSTAT : Reset was initiated by a Watchdog Timer Reset.
bits : 6 - 12 (7 bit)
access : read-write



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