\n
address_offset : 0x0 Bytes (0x0)
size : 0x414 byte (0x0)
mem_usage : registers
protection :
FIFO Access Port
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO direct access. Only locations 0 - 3F will return valid information.
bits : 0 - 31 (32 bit)
access : read-write
FIFO size and remaining slots open values
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO0SIZ : The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)
bits : 0 - 7 (8 bit)
access : read-write
FIFO0REM : The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)
bits : 8 - 23 (16 bit)
access : read-write
FIFO1SIZ : The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)
bits : 16 - 39 (24 bit)
access : read-write
FIFO1REM : The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)
bits : 24 - 55 (32 bit)
access : read-write
FIFO Threshold Configuration
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFORTHR : FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations.
bits : 0 - 5 (6 bit)
access : read-write
FIFOWTHR : FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations.
bits : 8 - 21 (14 bit)
access : read-write
FIFO POP register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFODOUT : This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.
bits : 0 - 31 (32 bit)
access : read-write
FIFO PUSH register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFODIN : This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).
bits : 0 - 31 (32 bit)
access : read-write
FIFO Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POPWR : Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode.
bits : 0 - 0 (1 bit)
access : read-write
FIFORSTN : Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset.
bits : 1 - 2 (2 bit)
access : read-write
FIFO Pointers
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOWPTR : Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.
bits : 0 - 3 (4 bit)
access : read-write
FIFORPTR : Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.
bits : 8 - 19 (12 bit)
access : read-write
I/O Clock Configuration
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOCLKEN : Enable for the interface clock. Must be enabled prior to executing any IO operations.
bits : 0 - 0 (1 bit)
access : read-write
FSEL : Select the input clock frequency.
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : MIN_PWR
Selects the minimum power clock. This setting should be used whenever the IOM is not active.
1 : HFRC
Selects the HFRC as the input clock.
2 : HFRC_DIV2
Selects the HFRC / 2 as the input clock.
3 : HFRC_DIV4
Selects the HFRC / 4 as the input clock.
4 : HFRC_DIV8
Selects the HFRC / 8 as the input clock.
5 : HFRC_DIV16
Selects the HFRC / 16 as the input clock.
6 : HFRC_DIV32
Selects the HFRC / 32 as the input clock.
7 : HFRC_DIV64
Selects the HFRC / 64 as the input clock.
End of enumeration elements list.
CLK32KEN : Enable for the 32Khz clock to the BLE module
bits : 11 - 22 (12 bit)
access : read-write
DIV3 : Enable of the divide by 3 of the source IOCLK.
bits : 12 - 24 (13 bit)
access : read-write
Command and offset Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Command for submodule.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
1 : WRITE
Write command using count of offset bytes specified in the OFFSETCNT field
2 : READ
Read command using count of offset bytes specified in the OFFSETCNT field
End of enumeration elements list.
OFFSETCNT : Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.
bits : 5 - 11 (7 bit)
access : read-write
CONT : Contine to hold the bus after the current transaction if set to a 1 with a new command issued.
bits : 7 - 14 (8 bit)
access : read-write
TSIZE : Defines the transaction size in bytes. The offset transfer is not included in this size.
bits : 8 - 27 (20 bit)
access : read-write
CMDSEL : Command Specific selection information
bits : 20 - 41 (22 bit)
access : read-write
OFFSETLO : This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first.
bits : 24 - 55 (32 bit)
access : read-write
Command Repeat Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDRPT : Count of number of times to repeat the next command.
bits : 0 - 4 (5 bit)
access : read-write
High order offset bytes
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETHI : Holds the high order bytes of the 2 or 3 byte offset phase of a transaction.
bits : 0 - 15 (16 bit)
access : read-write
Command status
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCMD : current command that is being executed
bits : 0 - 4 (5 bit)
access : read-write
CMDSTAT : The current status of the command execution.
bits : 5 - 12 (8 bit)
access : read-write
Enumeration:
1 : ERR
Error encountered with command
2 : ACTIVE
Actively processing command
4 : IDLE
Idle state, no active command, no error
6 : WAIT
Command in progress, but waiting on data from host
End of enumeration elements list.
CTSIZE : The current number of bytes still to be transferred with this command. This field will count down to zero.
bits : 8 - 27 (20 bit)
access : read-write
IO Master Interrupts: Enable
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
B2MST : B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
BLECIRQ : BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.
bits : 7 - 14 (8 bit)
access : read-write
BLECSSTAT : BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.
bits : 8 - 16 (9 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 9 - 18 (10 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 10 - 20 (11 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 11 - 22 (12 bit)
access : read-write
CQUPD : Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 12 - 24 (13 bit)
access : read-write
CQERR : Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions
bits : 13 - 26 (14 bit)
access : read-write
B2MSLEEP : The B2M_STATE from the BLE Core transitioned into the sleep state
bits : 14 - 28 (15 bit)
access : read-write
B2MACTIVE : Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)
bits : 15 - 30 (16 bit)
access : read-write
B2MSHUTDN : Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)
bits : 16 - 32 (17 bit)
access : read-write
IO Master Interrupts: Status
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
B2MST : B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
BLECIRQ : BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.
bits : 7 - 14 (8 bit)
access : read-write
BLECSSTAT : BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.
bits : 8 - 16 (9 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 9 - 18 (10 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 10 - 20 (11 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 11 - 22 (12 bit)
access : read-write
CQUPD : Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 12 - 24 (13 bit)
access : read-write
CQERR : Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions
bits : 13 - 26 (14 bit)
access : read-write
B2MSLEEP : The B2M_STATE from the BLE Core transitioned into the sleep state
bits : 14 - 28 (15 bit)
access : read-write
B2MACTIVE : Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)
bits : 15 - 30 (16 bit)
access : read-write
B2MSHUTDN : Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)
bits : 16 - 32 (17 bit)
access : read-write
IO Master Interrupts: Clear
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
B2MST : B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
BLECIRQ : BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.
bits : 7 - 14 (8 bit)
access : read-write
BLECSSTAT : BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.
bits : 8 - 16 (9 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 9 - 18 (10 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 10 - 20 (11 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 11 - 22 (12 bit)
access : read-write
CQUPD : Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 12 - 24 (13 bit)
access : read-write
CQERR : Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions
bits : 13 - 26 (14 bit)
access : read-write
B2MSLEEP : The B2M_STATE from the BLE Core transitioned into the sleep state
bits : 14 - 28 (15 bit)
access : read-write
B2MACTIVE : Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)
bits : 15 - 30 (16 bit)
access : read-write
B2MSHUTDN : Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)
bits : 16 - 32 (17 bit)
access : read-write
IO Master Interrupts: Set
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
B2MST : B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
BLECIRQ : BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.
bits : 7 - 14 (8 bit)
access : read-write
BLECSSTAT : BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.
bits : 8 - 16 (9 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 9 - 18 (10 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 10 - 20 (11 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 11 - 22 (12 bit)
access : read-write
CQUPD : Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 12 - 24 (13 bit)
access : read-write
CQERR : Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions
bits : 13 - 26 (14 bit)
access : read-write
B2MSLEEP : The B2M_STATE from the BLE Core transitioned into the sleep state
bits : 14 - 28 (15 bit)
access : read-write
B2MACTIVE : Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is de-asserted (1 -> 0)
bits : 15 - 30 (16 bit)
access : read-write
B2MSHUTDN : Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is de-asserted (1 -> 0)
bits : 16 - 32 (17 bit)
access : read-write
DMA Trigger Enable Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMDCMPEN : Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed.
bits : 0 - 0 (1 bit)
access : read-write
DTHREN : Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the commmand. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete.
bits : 1 - 2 (2 bit)
access : read-write
DMA Trigger Status Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMDCMP : Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.
bits : 0 - 0 (1 bit)
access : read-write
DTHR : Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 1 - 2 (2 bit)
access : read-write
DTOTCMP : DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.
bits : 2 - 4 (3 bit)
access : read-write
DMA Configuration Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable DMA Function
1 : EN
Enable DMA Function
End of enumeration elements list.
DMADIR : Direction
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : P2M
Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices.
1 : M2P
Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices.
End of enumeration elements list.
DMAPRI : Sets the Priority of the DMA request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : LOW
Low Priority (service as best effort)
1 : HIGH
High Priority (service immediately)
End of enumeration elements list.
DPWROFF : Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Power off disabled
1 : EN
Power off enabled
End of enumeration elements list.
DMA Total Transfer Count
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOTCOUNT : Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 0 - 11 (12 bit)
access : read-write
DMA Target Address Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TARGADDR : Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
bits : 0 - 19 (20 bit)
access : read-write
TARGADDR28 : Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash
bits : 28 - 56 (29 bit)
access : read-write
DMA Status Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATIP : DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write
DMACPL : DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0.
bits : 1 - 2 (2 bit)
access : read-write
DMAERR : DMA Error. This active high bit signals that an error was encountered during the DMA operation.
bits : 2 - 4 (3 bit)
access : read-write
Command Queue Configuration Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQEN : Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable CQ Function
1 : EN
Enable CQ Function
End of enumeration elements list.
CQPRI : Sets the Priority of the command queue dma request.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : LOW
Low Priority (service as best effort)
1 : HIGH
High Priority (service immediately)
End of enumeration elements list.
CQ Target Read Address Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQADDR : Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary
bits : 2 - 21 (20 bit)
access : read-write
CQADDR28 : Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access
bits : 28 - 56 (29 bit)
access : read-write
Command Queue Status Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQTIP : Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.
bits : 0 - 0 (1 bit)
access : read-write
CQPAUSED : Command queue operation is currently paused.
bits : 1 - 2 (2 bit)
access : read-write
CQERR : Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.
bits : 2 - 4 (3 bit)
access : read-write
Command Queue Flag Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQFLAGS : Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.
bits : 0 - 15 (16 bit)
access : read-write
CQIRQMASK : Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE
bits : 16 - 47 (32 bit)
access : read-write
Command Queue Flag Set/Clear Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQFSET : Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 0 - 7 (8 bit)
access : read-write
CQFTGL : Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 8 - 23 (16 bit)
access : read-write
CQFCLR : Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field
bits : 16 - 39 (24 bit)
access : read-write
Command Queue Pause Enable Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQPEN : Enables the specified event to pause command processing when active
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
32768 : CNTEQ
Pauses command queue processing when HWCNT matches SWCNT
16384 : BLEXOREN
Pause command queue when input BLE bit XORed with SWFLAG4 is '1'
8192 : IOMXOREN
Pause command queue when input IOM bit XORed with SWFLAG3 is '1'
4096 : GPIOXOREN
Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1'
2048 : MSPI1XNOREN
Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1'
1024 : MSPI0XNOREN
Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1'
512 : MSPI1XOREN
Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1'
256 : MSPI0XOREN
Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1'
128 : SWFLAGEN7
Pause the command queue when software flag bit 7 is '1'.
64 : SWFLAGEN6
Pause the command queue when software flag bit 7 is '1'
32 : SWFLAGEN5
Pause the command queue when software flag bit 7 is '1'
16 : SWFLAGEN4
Pause the command queue when software flag bit 7 is '1'
8 : SWFLAGEN3
Pause the command queue when software flag bit 7 is '1'
4 : SWFLAGEN2
Pause the command queue when software flag bit 7 is '1'
2 : SWFLAGEN1
Pause the command queue when software flag bit 7 is '1'
1 : SWFLGEN0
Pause the command queue when software flag bit 7 is '1'
End of enumeration elements list.
IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQCURIDX : Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write
IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQENDIDX : Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write
IOM Module Status Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : Bit has been deprecated. Please refer to the other error indicators. This will always return 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ERROR
Bit has been deprecated and will always return 0.
End of enumeration elements list.
CMDACT : Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : ACTIVE
An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed.
End of enumeration elements list.
IDLEST : indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : IDLE
The I/O state machine is in the idle state.
End of enumeration elements list.
SPI module master configuration
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOL : This bit selects SPI polarity.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CLK_BASE_0
The initial value of the clock is 0.
1 : CLK_BASE_1
The initial value of the clock is 1.
End of enumeration elements list.
SPHA : Selects the SPI phase When 1, will shift the sampling edge by 1/2 clock.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : SAMPLE_LEADING_EDGE
Sample on the leading (first) clock edge, rising or falling dependant on the value of SPOL
1 : SAMPLE_TRAILING_EDGE
Sample on the trailing (second) clock edge, rising of falling dependant on the value of SPOL
End of enumeration elements list.
FULLDUP : Full Duplex mode. Capture read data during writes operations
bits : 2 - 4 (3 bit)
access : read-write
WTFC : Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Write mode flow control disabled.
1 : EN
Write mode flow control enabled.
End of enumeration elements list.
RDFC : Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : DIS
Read mode flow control disabled.
1 : EN
Read mode flow control enabled.
End of enumeration elements list.
WTFCPOL : Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : NORMAL
SPI_STATUS signal from BLE Core high(1) creates flow control and new write spi transactions will not be started until the signal goes low.(default)
1 : INVERTED
SPI_STATUS signal from BLE Core high(1) creates low(0) control and new write spi transactions will not be started until the signal goes high.
End of enumeration elements list.
RDFCPOL : Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is de-asserted.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : NORMAL
SPI_STATUS signal from BLE Core high(1) creates flow control and new read spi transactions will not be started until the signal goes low.(default)
1 : INVERTED
SPI_STATUS signal from BLE Core low(0) creates flow control and new read spi transactions will not be started until the signal goes high.
End of enumeration elements list.
SPILSB : Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : MSB
Send and receive MSB bit first
1 : LSB
Send and receive LSB bit first
End of enumeration elements list.
DINDLY : Delay tap to use for the input signal (MISO). This gives more hold time on the input data.
bits : 24 - 50 (27 bit)
access : read-write
DOUTDLY : Delay tap to use for the output signal (MOSI). This give more hold time on the output data.
bits : 27 - 56 (30 bit)
access : read-write
MSPIRST : Bit is deprecated. setting it will have no effect.
bits : 30 - 60 (31 bit)
access : read-write
BLE Core Control
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRSMEN : Enable the power state machine for automatic sequencing and control of power states of the BLE Core module.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ON
Internal power state machine is enabled and will sequence the BLEH power domain as indicated in the design document. Overrides for the power signals are not enabled.
0 : OFF
Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals
End of enumeration elements list.
BLERSTN : Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : ACTIVE
The reset signal is active (0)
0 : INACTIVE
The reset signal is inactive (1)
End of enumeration elements list.
WAKEUPCTL : WAKE signal override. Controls the source of the WAKE signal to the BLE Core.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
3 : ON
Wake signal is set to on (1).
2 : OFF
Wake signal is set to off (0).
0 : AUTO
Wake signal is controlled by the PWRSM logic and automatically controlled
End of enumeration elements list.
DCDCFLGCTL : DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
3 : ON
DCDC Flag signal is set to on (1).
2 : OFF
DCDC Flag signal is set to off (0).
0 : AUTO
DCDC Flag signal is controlled by the PWRSM logic and automatically controlled
End of enumeration elements list.
BLEHREQCTL : BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
3 : ON
BLEH Power-on reg signal is set to on (1).
2 : OFF
BLEH Power-on signal is set to off (0).
0 : AUTO
BLEH Power-on signal is controlled by the PWRSM logic and automatically controlled
End of enumeration elements list.
WT4ACTOFF : Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for dcdc req from BLE Core.
bits : 8 - 16 (9 bit)
access : read-write
MCUFRCSLP : Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine.
bits : 9 - 18 (10 bit)
access : read-write
FRCCLK : Force the clock in the BLEIF to be always running
bits : 10 - 20 (11 bit)
access : read-write
STAYASLEEP : Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state.
bits : 11 - 22 (12 bit)
access : read-write
PWRISOCTL : Configuration of BLEH isolation control for power related signals.
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
3 : ON
BLEH power signal isolation to on (isolated).
2 : OFF
BLEH power signal isolation to off (not isolated).
0 : AUTO
BLEH Power signal isolation is controlled automatically through the interface logic
End of enumeration elements list.
SPIISOCTL : Configuration of BLEH isolation controls for SPI related signals.
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
3 : ON
SPI signals from BLE Core to/from MCU Core are isolated.
2 : OFF
SPI signals from BLE Core to/from MCU Core are not isolated.
0 : AUTO
SPI signals from BLE Core to/from MCU Core are automatically isolated by the logic
End of enumeration elements list.
BLE Power command interface
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEREQ : Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state
bits : 0 - 0 (1 bit)
access : read-write
RESTART : Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state.
bits : 1 - 2 (2 bit)
access : read-write
BLE Core status
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B2MSTATE : State of the BLE Core logic.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : RESET
Reset State
1 : Sleep
Sleep state.
2 : Standby
Standby State
3 : Idle
Idle state
4 : Active
Active state.
End of enumeration elements list.
SPISTATUS : Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active.
bits : 3 - 6 (4 bit)
access : read-write
DCDCREQ : Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1.
bits : 4 - 8 (5 bit)
access : read-write
DCDCFLAG : Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH ppower is active.
bits : 5 - 10 (6 bit)
access : read-write
WAKEUP : Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state.
bits : 6 - 12 (7 bit)
access : read-write
BLEIRQ : Status of the BLEIRQ signal from the BLE Core. A value of 1 idicates that read data is available in the core and a read operation needs to be performed.
bits : 7 - 14 (8 bit)
access : read-write
PWRST : Current status of the power state machine
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : OFF
Internal power state machine is disabled and will not sequence the BLEH power domain. The values of the overrides will be used to drive the output sequencing signals
1 : INIT
Initialization state. BLEH not powered
2 : PWRON
Waiting for the powerup of the BLEH
3 : ACTIVE
The BLE Core is powered and active
6 : SLEEP
The BLE Core has entered sleep mode and the power request is inactive
4 : SHUTDOWN
The BLE Core is in shutdown mode
End of enumeration elements list.
BLEHACK : Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use.
bits : 11 - 22 (12 bit)
access : read-write
BLEHREQ : Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use.
bits : 12 - 24 (13 bit)
access : read-write
BLEIF Master Debug Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGEN : Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings
bits : 0 - 0 (1 bit)
access : read-write
IOCLKON : IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 1 - 2 (2 bit)
access : read-write
APBCLKON : APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 2 - 4 (3 bit)
access : read-write
DBGDATA : Debug data
bits : 3 - 34 (32 bit)
access : read-write
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