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CACHECTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x240 byte (0x0)
mem_usage : registers
protection :

Registers

CACHECFG

NCR0START

NCR0END

NCR1START

NCR1END

FLASHCFG

DMON0

DMON1

DMON2

DMON3

IMON0

IMON1

IMON2

IMON3

CTRL


CACHECFG

Flash Cache Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACHECFG CACHECFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE LRU ENABLE_NC0 ENABLE_NC1 CONFIG ICACHE_ENABLE DCACHE_ENABLE CACHE_CLKGATE CACHE_LS DATA_CLKGATE ENABLE_MONITOR

ENABLE : Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access.
bits : 0 - 0 (1 bit)
access : read-write

LRU : Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM.
bits : 1 - 2 (2 bit)
access : read-write

ENABLE_NC0 : Enable Non-cacheable region 0. See NCR0 registers to define the region.
bits : 2 - 4 (3 bit)
access : read-write

ENABLE_NC1 : Enable Non-cacheable region 1. See NCR1 registers to define the region.
bits : 3 - 6 (4 bit)
access : read-write

CONFIG : Sets the cache configuration
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

4 : W1_128B_512E

Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active)

5 : W2_128B_512E

Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active)

8 : W1_128B_1024E

Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active)

End of enumeration elements list.

ICACHE_ENABLE : Enable Flash Instruction Caching
bits : 8 - 16 (9 bit)
access : read-write

DCACHE_ENABLE : Enable Flash Data Caching.
bits : 9 - 18 (10 bit)
access : read-write

CACHE_CLKGATE : Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency.
bits : 10 - 20 (11 bit)
access : read-write

CACHE_LS : Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage.
bits : 11 - 22 (12 bit)
access : read-write

DATA_CLKGATE : Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency.
bits : 20 - 40 (21 bit)
access : read-write

ENABLE_MONITOR : Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments.
bits : 24 - 48 (25 bit)
access : read-write


NCR0START

Flash Cache Noncachable Region 0 Start
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR0START NCR0START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Start address for non-cacheable region 0
bits : 4 - 30 (27 bit)
access : read-write


NCR0END

Flash Cache Noncachable Region 0 End
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR0END NCR0END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : End address for non-cacheable region 0
bits : 4 - 30 (27 bit)
access : read-write


NCR1START

Flash Cache Noncachable Region 1 Start
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR1START NCR1START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Start address for non-cacheable region 1
bits : 4 - 30 (27 bit)
access : read-write


NCR1END

Flash Cache Noncachable Region 1 End
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR1END NCR1END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : End address for non-cacheable region 1
bits : 4 - 30 (27 bit)
access : read-write


FLASHCFG

Flash Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCFG FLASHCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_WAIT SEDELAY LPM_RD_WAIT LPMMODE

RD_WAIT : Sets read waitstates for normal (fast) operation. A value of 1 is recommended.
bits : 0 - 3 (4 bit)
access : read-write

SEDELAY : Sets SE delay (flash address setup). A value of 5 is recommended.
bits : 4 - 10 (7 bit)
access : read-write

LPM_RD_WAIT : Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)
bits : 8 - 19 (12 bit)
access : read-write

LPMMODE : Controls flash low power modes (control of LPM pin).
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

0 : NEVER

High power mode (LPM not used).

1 : STANDBY

Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE.

2 : ALWAYS

Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times.

End of enumeration elements list.


DMON0

Data Cache Total Accesses
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMON0 DMON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACCESS_COUNT

DACCESS_COUNT : Total accesses to data cache. All performance metrics should be relative to the number of accesses performed.
bits : 0 - 31 (32 bit)
access : read-write


DMON1

Data Cache Tag Lookups
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMON1 DMON1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLOOKUP_COUNT

DLOOKUP_COUNT : Total tag lookups from data cache.
bits : 0 - 31 (32 bit)
access : read-write


DMON2

Data Cache Hits
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMON2 DMON2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHIT_COUNT

DHIT_COUNT : Cache hits from lookup operations.
bits : 0 - 31 (32 bit)
access : read-write


DMON3

Data Cache Line Hits
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMON3 DMON3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLINE_COUNT

DLINE_COUNT : Cache hits from line cache
bits : 0 - 31 (32 bit)
access : read-write


IMON0

Instruction Cache Total Accesses
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMON0 IMON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACCESS_COUNT

IACCESS_COUNT : Total accesses to Instruction cache
bits : 0 - 31 (32 bit)
access : read-write


IMON1

Instruction Cache Tag Lookups
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMON1 IMON1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILOOKUP_COUNT

ILOOKUP_COUNT : Total tag lookups from Instruction cache
bits : 0 - 31 (32 bit)
access : read-write


IMON2

Instruction Cache Hits
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMON2 IMON2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IHIT_COUNT

IHIT_COUNT : Cache hits from lookup operations
bits : 0 - 31 (32 bit)
access : read-write


IMON3

Instruction Cache Line Hits
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMON3 IMON3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILINE_COUNT

ILINE_COUNT : Cache hits from line cache
bits : 0 - 31 (32 bit)
access : read-write


CTRL

Cache Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVALIDATE RESET_STAT CACHE_READY FLASH0_SLM_STATUS FLASH0_SLM_DISABLE FLASH0_SLM_ENABLE FLASH1_SLM_STATUS FLASH1_SLM_DISABLE FLASH1_SLM_ENABLE

INVALIDATE : Writing a 1 to this bitfield invalidates the flash cache contents.
bits : 0 - 0 (1 bit)
access : read-write

RESET_STAT : Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : CLEAR

Clear Cache Stats

End of enumeration elements list.

CACHE_READY : Cache Ready Status (enabled and not processing an invalidate operation)
bits : 2 - 4 (3 bit)
access : read-write

FLASH0_SLM_STATUS : Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode.
bits : 4 - 8 (5 bit)
access : read-write

FLASH0_SLM_DISABLE : Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it).
bits : 5 - 10 (6 bit)
access : read-write

FLASH0_SLM_ENABLE : Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.
bits : 6 - 12 (7 bit)
access : read-write

FLASH1_SLM_STATUS : Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode.
bits : 8 - 16 (9 bit)
access : read-write

FLASH1_SLM_DISABLE : Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it).
bits : 9 - 18 (10 bit)
access : read-write

FLASH1_SLM_ENABLE : Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.
bits : 10 - 20 (11 bit)
access : read-write



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