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CLKGEN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection :

Registers

CALXT

CLKOUT

INTRPTEN

INTRPTSTAT

INTRPTCLR

INTRPTSET

CLKKEY

CCTRL

STATUS

HFADJ

CLOCKENSTAT

CLOCKEN2STAT

CLOCKEN3STAT

FREQCTRL

BLEBUCKTONADJ

CALRC

ACALCTR

OCTRL


CALXT

XT Oscillator Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALXT CALXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALXT

CALXT : XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023.
bits : 0 - 10 (11 bit)
access : read-write


CLKOUT

CLKOUT Frequency Select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUT CLKOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKEN

CKSEL : CLKOUT signal select
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : LFRC

LFRC

1 : XT_DIV2

XT / 2

2 : XT_DIV4

XT / 4

3 : XT_DIV8

XT / 8

4 : XT_DIV16

XT / 16

5 : XT_DIV32

XT / 32

16 : RTC_1Hz

1 Hz as selected in RTC

22 : XT_DIV2M

XT / 2^21

23 : XT

XT

24 : CG_100Hz

100 Hz as selected in CLKGEN

25 : HFRC

HFRC

26 : HFRC_DIV4

HFRC / 4

27 : HFRC_DIV8

HFRC / 8

28 : HFRC_DIV16

HFRC / 16

29 : HFRC_DIV64

HFRC / 64

30 : HFRC_DIV128

HFRC / 128

31 : HFRC_DIV256

HFRC / 256

32 : HFRC_DIV512

HFRC / 512

34 : FLASH_CLK

Flash Clock

35 : LFRC_DIV2

LFRC / 2

36 : LFRC_DIV32

LFRC / 32

37 : LFRC_DIV512

LFRC / 512

38 : LFRC_DIV32K

LFRC / 32768

39 : XT_DIV256

XT / 256

40 : XT_DIV8K

XT / 8192

41 : XT_DIV64K

XT / 2^16

42 : ULFRC_DIV16

Uncal LFRC / 16

43 : ULFRC_DIV128

Uncal LFRC / 128

44 : ULFRC_1Hz

Uncal LFRC / 1024

45 : ULFRC_DIV4K

Uncal LFRC / 4096

46 : ULFRC_DIV1M

Uncal LFRC / 2^20

47 : HFRC_DIV64K

HFRC / 2^16

48 : HFRC_DIV16M

HFRC / 2^24

49 : LFRC_DIV1M

LFRC / 2^20

50 : HFRCNE

HFRC (not autoenabled)

51 : HFRCNE_DIV8

HFRC / 8 (not autoenabled)

53 : XTNE

XT (not autoenabled)

54 : XTNE_DIV16

XT / 16 (not autoenabled)

55 : LFRCNE_DIV32

LFRC / 32 (not autoenabled)

57 : LFRCNE

LFRC (not autoenabled) - Default for undefined values

End of enumeration elements list.

CKEN : Enable the CLKOUT signal
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : DIS

Disable CLKOUT

1 : EN

Enable CLKOUT

End of enumeration elements list.


INTRPTEN

CLKGEN Interrupt Register: Enable
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRPTEN INTRPTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write


INTRPTSTAT

CLKGEN Interrupt Register: Status
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRPTSTAT INTRPTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write


INTRPTCLR

CLKGEN Interrupt Register: Clear
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRPTCLR INTRPTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write


INTRPTSET

CLKGEN Interrupt Register: Set
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRPTSET INTRPTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF ACC OF

ACF : Autocalibration Fail interrupt
bits : 0 - 0 (1 bit)
access : read-write

ACC : Autocalibration Complete interrupt
bits : 1 - 2 (2 bit)
access : read-write

OF : XT Oscillator Fail interrupt
bits : 2 - 4 (3 bit)
access : read-write


CLKKEY

Key Register for Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKKEY CLKKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKKEY

CLKKEY : Key register value.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

71 : Key

Key

End of enumeration elements list.


CCTRL

HFRC Clock Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTRL CCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORESEL

CORESEL : Core Clock divisor
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HFRC

Core Clock is HFRC

1 : HFRC_DIV2

Core Clock is HFRC / 2

End of enumeration elements list.


STATUS

Clock Generator Status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OMODE OSCF

OMODE : Current RTC oscillator (1 => LFRC, 0 => XT). After an RTC oscillator change, it may take up to 2 seconds for this field to reflect the new oscillator.
bits : 0 - 0 (1 bit)
access : read-write

OSCF : XT Oscillator is enabled but not oscillating
bits : 1 - 2 (2 bit)
access : read-write


HFADJ

HFRC Adjustment
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFADJ HFADJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFADJEN HFADJCK HFXTADJ HFWARMUP HFADJGAIN

HFADJEN : HFRC adjustment control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable the HFRC adjustment

1 : EN

Enable the HFRC adjustment

End of enumeration elements list.

HFADJCK : Repeat period for HFRC adjustment
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0 : 4SEC

Autoadjust repeat period = 4 seconds

1 : 16SEC

Autoadjust repeat period = 16 seconds

2 : 32SEC

Autoadjust repeat period = 32 seconds

3 : 64SEC

Autoadjust repeat period = 64 seconds

4 : 128SEC

Autoadjust repeat period = 128 seconds

5 : 256SEC

Autoadjust repeat period = 256 seconds

6 : 512SEC

Autoadjust repeat period = 512 seconds

7 : 1024SEC

Autoadjust repeat period = 1024 seconds

End of enumeration elements list.

HFXTADJ : Target HFRC adjustment value.
bits : 8 - 27 (20 bit)
access : read-write

HFWARMUP : XT warmup period for HFRC adjustment
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : 1SEC

Autoadjust XT warmup period = 1-2 seconds

1 : 2SEC

Autoadjust XT warmup period = 2-4 seconds

End of enumeration elements list.

HFADJGAIN : Gain control for HFRC adjustment
bits : 21 - 44 (24 bit)
access : read-write

Enumeration:

0 : Gain_of_1

HF Adjust with Gain of 1

1 : Gain_of_1_in_2

HF Adjust with Gain of 0.5

2 : Gain_of_1_in_4

HF Adjust with Gain of 0.25

3 : Gain_of_1_in_8

HF Adjust with Gain of 0.125

4 : Gain_of_1_in_16

HF Adjust with Gain of 0.0625

5 : Gain_of_1_in_32

HF Adjust with Gain of 0.03125

End of enumeration elements list.


CLOCKENSTAT

Clock Enable Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKENSTAT CLOCKENSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKENSTAT

CLOCKENSTAT : Clock enable status
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

1 : ADC_CLKEN

Clock enable for the ADC.

2 : APBDMA_ACTIVITY_CLKEN

Clock enable for the APBDMA ACTIVITY

4 : APBDMA_AOH_CLKEN

Clock enable for the APBDMA AOH DOMAIN

8 : APBDMA_AOL_CLKEN

Clock enable for the APBDMA AOL DOMAIN

16 : APBDMA_APB_CLKEN

Clock enable for the APBDMA_APB

32 : APBDMA_BLEL_CLKEN

Clock enable for the APBDMA_BLEL

64 : APBDMA_HCPA_CLKEN

Clock enable for the APBDMA_HCPA

128 : APBDMA_HCPB_CLKEN

Clock enable for the APBDMA_HCPB

256 : APBDMA_HCPC_CLKEN

Clock enable for the APBDMA_HCPC

512 : APBDMA_MSPI_CLKEN

Clock enable for the APBDMA_MSPI

1024 : APBDMA_PDM_CLKEN

Clock enable for the APBDMA_PDM

2048 : BLEIF_CLK_CLKEN

Clock enable for the BLEIF

4096 : BLEIF_CLK32K_CLKEN

Clock enable for the BLEIF 32khZ CLOCK

8192 : CTIMER_CLKEN

Clock enable for the CTIMER BLOCK

16384 : CTIMER0A_CLKEN

Clock enable for the CTIMER0A

32768 : CTIMER0B_CLKEN

Clock enable for the CTIMER0B

65536 : CTIMER1A_CLKEN

Clock enable for the CTIMER1A

131072 : CTIMER1B_CLKEN

Clock enable for the CTIMER1B

262144 : CTIMER2A_CLKEN

Clock enable for the CTIMER2A

524288 : CTIMER2B_CLKEN

Clock enable for the CTIMER2B

1048576 : CTIMER3A_CLKEN

Clock enable for the CTIMER3A

2097152 : CTIMER3B_CLKEN

Clock enable for the CTIMER3B

4194304 : CTIMER4A_CLKEN

Clock enable for the CTIMER4A

8388608 : CTIMER4B_CLKEN

Clock enable for the CTIMER4B

16777216 : CTIMER5A_CLKEN

Clock enable for the CTIMER5A

33554432 : CTIMER5B_CLKEN

Clock enable for the CTIMER5B

67108864 : CTIMER6A_CLKEN

Clock enable for the CTIMER6A

134217728 : CTIMER6B_CLKEN

Clock enable for the CTIMER6B

268435456 : CTIMER7A_CLKEN

Clock enable for the CTIMER7A

536870912 : CTIMER7B_CLKEN

Clock enable for the CTIMER7B

1073741824 : DAP_CLKEN

Clock enable for the DAP

2147483648 : IOMSTRIFC0_CLKEN

Clock enable for the IOMSTRIFC0

End of enumeration elements list.


CLOCKEN2STAT

Clock Enable Status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKEN2STAT CLOCKEN2STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKEN2STAT

CLOCKEN2STAT : Clock enable status 2
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

1 : IOMSTRIFC1_CLKEN

Clock enable for the IO MASTER 1 IFC INTERFACE

2 : IOMSTRIFC2_CLKEN

Clock enable for the IO MASTER 2 IFC INTERFACE

4 : IOMSTRIFC3_CLKEN

Clock enable for the IO MASTER 3 IFC INTERFACE

8 : IOMSTRIFC4_CLKEN

Clock enable for the IO MASTER 4 IFC INTERFACE

16 : IOMSTRIFC5_CLKEN

Clock enable for the IO MASTER 5 IFC INTERFACE

32 : PDM_CLKEN

Clock enable for the PDM

64 : PDMIFC_CLKEN

Clock enable for the PDM INTERFACE

128 : PWRCTRL_CLKEN

Clock enable for the PWRCTRL

256 : PWRCTRL_COUNT_CLKEN

Clock enable for the PWRCTRL counter

512 : RSTGEN_CLKEN

Clock enable for the RSTGEN

1024 : SCARD_CLKEN

Clock enable for the SCARD

2048 : SCARD_ALTAPB_CLKEN

Clock enable for the SCARD ALTAPB

4096 : STIMER_CNT_CLKEN

Clock enable for the STIMER_CNT_CLKEN

8192 : TPIU_CLKEN

Clock enable for the TPIU_CLKEN

16384 : UART0HF_CLKEN

Clock enable for the UART0 HF

32768 : UART1HF_CLKEN

Clock enable for the UART1 HF

1073741824 : XT_32KHZ_EN

Clock enable for the XT 32KHZ

2147483648 : FORCEHFRC

HFRC is forced on Status.

End of enumeration elements list.


CLOCKEN3STAT

Clock Enable Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCKEN3STAT CLOCKEN3STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOCKEN3STAT

CLOCKEN3STAT : Clock enable status 3
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

131072 : DAP_enabled

DAP clock is enabled [17]

262144 : VCOMP_enabled

VCOMP powerdown indicator [18]

16777216 : XTAL_enabled

XTAL is enabled [24]

33554432 : HFRC_enabled

HFRC is enabled [25]

67108864 : HFADJEN

HFRC Adjust enabled [26]

134217728 : HFRC_en_out

HFRC Enabled out [27]

268435456 : RTC_XT

RTC use XT [28]

536870912 : clkout_xtal_en

XTAL clkout enabled [29]

1073741824 : clkout_hfrc_en

HFRC clkout enabled [30]

2147483648 : flashclk_en

Flash clk is enabled [31]

End of enumeration elements list.


FREQCTRL

HFRC Frequency Control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQCTRL FREQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BURSTREQ BURSTACK BURSTSTATUS

BURSTREQ : Frequency Burst Enable Request
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Frequency for ARM core stays at 48MHz

1 : EN

Frequency for ARM core is increased to 96MHz

End of enumeration elements list.

BURSTACK : Frequency Burst Request Acknowledge. Frequency burst requested is always acknowledged whether burst is granted or not depending on feature enable.
bits : 1 - 2 (2 bit)
access : read-write

BURSTSTATUS : This represents frequency burst status.
bits : 2 - 4 (3 bit)
access : read-write


BLEBUCKTONADJ

BLE BUCK TON ADJUST
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLEBUCKTONADJ BLEBUCKTONADJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TONLOWTHRESHOLD TONHIGHTHRESHOLD TONADJUSTPERIOD TONADJUSTEN ZEROLENDETECTTRIM ZEROLENDETECTEN

TONLOWTHRESHOLD : TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)
bits : 0 - 9 (10 bit)
access : read-write

TONHIGHTHRESHOLD : TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)
bits : 10 - 29 (20 bit)
access : read-write

TONADJUSTPERIOD : TON ADJUST PERIOD
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

3 : HFRC_3KHz

Adjust done for every 1 3KHz period

2 : HFRC_12KHz

Adjust done for every 1 12KHz period

1 : HFRC_47KHz

Adjust done for every 1 47KHz period

0 : HFRC_94KHz

Adjust done for every 1 94KHz period

End of enumeration elements list.

TONADJUSTEN : TON ADJUST ENABLE
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

0 : DIS

Disable Adjust for BLE BUCK TON trim

1 : EN

Enable Adjust for BLE BUCK TON trim

End of enumeration elements list.

ZEROLENDETECTTRIM : BLEBUCK ZERO LENGTH DETECT TRIM
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

15 : SetF

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more

14 : SetE

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more

13 : SetD

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.2us (10 percent margin of error) or more

12 : SetC

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 64.8us (10 percent margin of error) or more

11 : SetB

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 59.4us (10 percent margin of error) or more

10 : SetA

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 54.0us (10 percent margin of error) or more

9 : Set9

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 48.6us (10 percent margin of error) or more

8 : Set8

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 43.2us (10 percent margin of error) or more

7 : Set7

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 37.8us (10 percent margin of error) or more

6 : Set6

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 32.4us (10 percent margin of error) or more

5 : Set5

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 27.0us (10 percent margin of error) or more

4 : Set4

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 21.6us (10 percent margin of error) or more

3 : Set3

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 16.2us (10 percent margin of error) or more

2 : Set2

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 10.8us (10 percent margin of error) or more

1 : Set1

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 5.4us (10 percent margin of error) or more

0 : Set0

Indicator send when the BLE BUCK asserts blebuck_comp1 for about 2.0us (10 percent margin of error) or more

End of enumeration elements list.

ZEROLENDETECTEN : BLEBUCK ZERO LENGTH DETECT ENABLE
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Disable Zero Length Detect

1 : EN

Enable Zero Length Detect

End of enumeration elements list.


CALRC

RC Oscillator Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALRC CALRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRC

CALRC : LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock.
bits : 0 - 17 (18 bit)
access : read-write


ACALCTR

Autocalibration Counter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACALCTR ACALCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACALCTR

ACALCTR : Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC.
bits : 0 - 23 (24 bit)
access : read-write


OCTRL

Oscillator Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCTRL OCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPXT STOPRC FOS OSEL ACAL

STOPXT : Stop the XT Oscillator to the RTC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : EN

Enable the XT Oscillator to drive the RTC

1 : STOP

Stop the XT Oscillator when driving the RTC

End of enumeration elements list.

STOPRC : Stop the LFRC Oscillator to the RTC
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : EN

Enable the LFRC Oscillator to drive the RTC

1 : STOP

Stop the LFRC Oscillator when driving the RTC

End of enumeration elements list.

FOS : Oscillator switch on failure function. If this is set, then LFRC clock source will switch from XT to RC.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : DIS

Disable the oscillator switch on failure function.

1 : EN

Enable the oscillator switch on failure function.

End of enumeration elements list.

OSEL : Selects the RTC oscillator (1 => LFRC, 0 => XT)
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : RTC_XT

RTC uses the XT

1 : RTC_LFRC

RTC uses the LFRC

End of enumeration elements list.

ACAL : Autocalibration control. This selects the source to be used in the autocalibration flow. This flow can also be used to measure an internal clock against an external clock source, with the external clock normally used as the reference.
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable Autocalibration

2 : 1024SEC

Autocalibrate every 1024 seconds. Once autocalibration is done, an interrupt will be triggered at the end of 1024 seconds.

3 : 512SEC

Autocalibrate every 512 seconds. Once autocalibration is done, an interrupt will be trigged at the end of 512 seconds.

6 : XTFREQ

Frequency measurement using XT. The XT clock is normally considered much more accurate than the LFRC clock source.

7 : EXTFREQ

Frequency measurement using external clock.

End of enumeration elements list.



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