\n

CTIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x310 byte (0x0)
mem_usage : registers
protection :

Registers

TMR0

GLOBEN

OUTCFG0

OUTCFG1

OUTCFG2

OUTCFG3

INCFG

CMPRAUXA0

STCFG

STTMR

CAPTURECONTROL

SCMPR0

SCMPR1

SCMPR2

SCMPR3

SCMPR4

SCMPR5

SCMPR6

SCMPR7

CMPRAUXB0

AUX0

SCAPT0

SCAPT1

SCAPT2

SCAPT3

SNVR0

SNVR1

SNVR2

SNVR3

TMR1

INTEN

INTSTAT

INTCLR

INTSET

CMPRA1

CMPRB1

CTRL1

STMINTEN

STMINTSTAT

STMINTCLR

STMINTSET

CMPRAUXA1

CMPRAUXB1

AUX1

CMPRA0

TMR2

CMPRA2

CMPRB2

CTRL2

CMPRAUXA2

CMPRAUXB2

AUX2

TMR3

CMPRA3

CMPRB3

CTRL3

CMPRAUXA3

CMPRAUXB3

AUX3

CMPRB0

TMR4

CMPRA4

CMPRB4

CTRL4

CMPRAUXA4

CMPRAUXB4

AUX4

TMR5

CMPRA5

CMPRB5

CTRL5

CMPRAUXA5

CMPRAUXB5

AUX5

CTRL0

TMR6

CMPRA6

CMPRB6

CTRL6

CMPRAUXA6

CMPRAUXB6

AUX6

TMR7

CMPRA7

CMPRB7

CTRL7

CMPRAUXA7

CMPRAUXB7

AUX7


TMR0

Counter/Timer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR0 TMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA0 CTTMRB0

CTTMRA0 : Counter/Timer A0.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB0 : Counter/Timer B0.
bits : 16 - 47 (32 bit)
access : read-write


GLOBEN

Counter/Timer Global Enable
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLOBEN GLOBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA0 ENB0 ENA1 ENB1 ENA2 ENB2 ENA3 ENB3 ENA4 ENB4 ENA5 ENB5 ENA6 ENB6 ENA7 ENB7

ENA0 : Alternate enable for A0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB0 : Alternate enable for B0
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA1 : Alternate enable for A1
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB1 : Alternate enable for B1
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA2 : Alternate enable for A2
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB2 : Alternate enable for B2
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA3 : Alternate enable for A3
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB3 : Alternate enable for B3.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA4 : Alternate enable for A4
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB4 : Alternate enable for B4
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA5 : Alternate enable for A5
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB5 : Alternate enable for B5
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA6 : Alternate enable for A6
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB6 : Alternate enable for B6
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENA7 : Alternate enable for A7
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.

ENB7 : Alternate enable for B7.
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

1 : LCO

Use local enable.

0 : DIS

Disable CTIMER.

End of enumeration elements list.


OUTCFG0

Counter/Timer Output Config 0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCFG0 OUTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9

CFG0 : Pad output 0 configuration
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A6OUT

Output is A6OUT.

4 : A5OUT2

Output is A5OUT2.

3 : B2OUT2

Output is B2OUT2.

2 : A0OUT

Output is A0OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG1 : Pad output 1 configuration
bits : 3 - 8 (6 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B7OUT2

Output is B7OUT2.

4 : A5OUT

Output is A5OUT.

3 : A0OUT

Output is A0OUT.

2 : A0OUT2

Output is A0OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG2 : Pad output 2 configuration
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A7OUT

Output is A7OUT.

4 : B6OUT2

Output is B6OUT2.

3 : B1OUT2

Output is B1OUT2.

2 : B0OUT

Output is B0OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG3 : Pad output 3 configuration
bits : 9 - 20 (12 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A6OUT

Output is A6OUT.

4 : A1OUT

Output is A1OUT.

3 : B0OUT

Output is B0OUT.

2 : B0OUT2

Output is B0OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG4 : Pad output 4 configuration
bits : 12 - 26 (15 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B5OUT

Output is B5OUT.

4 : A5OUT2

Output is A5OUT2.

3 : A2OUT2

Output is A2OUT2.

2 : A1OUT

Output is A1OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG5 : Pad output 5 configuration
bits : 16 - 34 (19 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A7OUT

Output is A7OUT.

4 : B6OUT

Output is A5OUT.

3 : A1OUT

Output is A1OUT.

2 : A1OUT2

Output is A1OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG6 : Pad output 6 configuration
bits : 19 - 40 (22 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B7OUT

Output is B7OUT.

4 : B5OUT2

Output is B5OUT2.

3 : A1OUT

Output is A1OUT.

2 : B1OUT

Output is B1OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG7 : Pad output 7 configuration
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A7OUT

Output is A7OUT.

4 : B5OUT

Output is B5OUT.

3 : B1OUT

Output is B1OUT.

2 : B1OUT2

Output is B1OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG8 : Pad output 8 configuration
bits : 25 - 52 (28 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B6OUT

Output is B6OUT.

4 : A4OUT2

Output is A4OUT2.

3 : A3OUT2

Output is A3OUT.

2 : A2OUT

Output is A2OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG9 : Pad output 9 configuration
bits : 28 - 58 (31 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B0OUT

Output is B0OUT.

4 : A4OUT

Output is A4OUT.

3 : A2OUT

Output is A2OUT.

2 : A2OUT2

Output is A2OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.


OUTCFG1

Counter/Timer Output Config 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCFG1 OUTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19

CFG10 : Pad output 10 configuration
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A6OUT

Output is A6OUT.

4 : B4OUT2

Output is B4OUT2.

3 : B3OUT2

Output is B3OUT2.

2 : B2OUT

Output is B2OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG11 : Pad output 11 configuration
bits : 3 - 8 (6 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B5OUT2

Output is B5OUT2.

4 : B4OUT

Output is B4OUT.

3 : B2OUT

Output is B2OUT.

2 : B2OUT2

Output is B2OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG12 : Pad output 12 configuration
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B6OUT2

Output is B6OUT2.

4 : B0OUT2

Output is B0OUT2.

3 : B1OUT

Output is B1OUT.

2 : A3OUT

Output is A3OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG13 : Pad output 13 configuration
bits : 9 - 20 (12 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B4OUT2

Output is B4OUT2.

4 : A6OUT

Output is A6OUT.

3 : A3OUT

Output is A3OUT.

2 : A3OUT2

Output is A3OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG14 : Pad output 14 configuration
bits : 12 - 26 (15 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A7OUT

Output is A7OUT.

4 : B7OUT2

Output is B7OUT2.

3 : B1OUT

Output is B1OUT.

2 : B3OUT

Output is B3OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG15 : Pad output 15 configuration
bits : 16 - 34 (19 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A4OUT2

Output is A4OUT2.

4 : A7OUT

Output is A7OUT.

3 : B3OUT

Output is B3OUT.

2 : B3OUT2

Output is B3OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG16 : Pad output 16 configuration
bits : 19 - 40 (22 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B3OUT2

Output is B3OUT2.

4 : A0OUT2

Output is A0OUT2.

3 : A0OUT

Output is A0OUT.

2 : A4OUT

Output is A4OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG17 : Pad output 17 configuration
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A1OUT2

Output is A1OUT2.

4 : A4OUT

Output is A4OUT.

3 : B7OUT

Output is B7OUT.

2 : A4OUT2

Output is A4OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG18 : Pad output 18 configuration
bits : 25 - 52 (28 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A3OUT2

Output is A3OUT2.

4 : A0OUT

Output is A0OUT.

3 : B0OUT

Output is B0OUT.

2 : B4OUT

Output is B4OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG19 : Pad output 19 configuration
bits : 28 - 58 (31 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B1OUT2

Output is B1OUT2.

4 : B4OUT

Output is B4OUT.

3 : A2OUT

Output is A2OUT.

2 : B4OUT2

Output is B4OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.


OUTCFG2

Counter/Timer Output Config 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCFG2 OUTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG20 CFG21 CFG22 CFG23 CFG24 CFG25 CFG26 CFG27 CFG28 CFG29

CFG20 : Pad output 20 configuration
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B2OUT2

Output is B2OUT2.

4 : A1OUT2

Output is A1OUT2.

3 : A1OUT

Output is A1OUT.

2 : A5OUT

Output is A5OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG21 : Pad output 21 configuration
bits : 3 - 8 (6 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A0OUT2

Output is A0OUT2.

4 : B5OUT

Output is B5OUT.

3 : A1OUT

Output is A1OUT.

2 : A5OUT2

Output is A5OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG22 : Pad output 22 configuration
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A2OUT2

Output is A2OUT2.

4 : A1OUT

Output is A1OUT.

3 : A6OUT

Output is A6OUT.

2 : B5OUT

Output is B5OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG23 : Pad output 23 configuration
bits : 9 - 20 (12 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B0OUT2

Output is B0OUT2.

4 : A5OUT

Output is A5OUT.

3 : A7OUT

Output is A7OUT.

2 : B5OUT2

Output is B5OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG24 : Pad output 24 configuration
bits : 12 - 26 (15 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B1OUT2

Output is B1OUT2.

4 : A1OUT

Output is A1OUT.

3 : A2OUT

Output is A2OUT.

2 : A6OUT

Output is A6OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG25 : Pad output 25 configuration
bits : 16 - 34 (19 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A2OUT2

Output is A2OUT2.

4 : A6OUT

Output is A6OUT.

3 : B2OUT

Output is B2OUT.

2 : B4OUT2

Output is B4OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG26 : Pad output 26 configuration
bits : 19 - 40 (22 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A1OUT2

Output is A1OUT2.

4 : A5OUT

Output is A5OUT.

3 : B2OUT

Output is B2OUT.

2 : B6OUT

Output is B6OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG27 : Pad output 27 configuration
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B2OUT2

Output is B2OUT2.

4 : B6OUT

Output is B6OUT.

3 : A1OUT

Output is A1OUT.

2 : B6OUT2

Output is B6OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG28 : Pad output 28 configuration
bits : 25 - 52 (28 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B0OUT2

Output is B0OUT2.

4 : A5OUT2

Output is A5OUT2.

3 : A3OUT

Output is A3OUT.

2 : A7OUT

Output is A7OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG29 : Pad output 29 configuration
bits : 28 - 58 (31 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A3OUT2

Output is A3OUT2.

4 : A7OUT

Output is A7OUT.

3 : A1OUT

Output is A1OUT.

2 : B5OUT2

Output is B5OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.


OUTCFG3

Counter/Timer Output Config 3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTCFG3 OUTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG30 CFG31

CFG30 : Pad output 30 configuration
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : A0OUT2

Output is A0OUT2.

4 : A4OUT2

Output is A4OUT2.

3 : B3OUT

Output is B3OUT.

2 : B7OUT

Output is B7OUT

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.

CFG31 : Pad output 31 configuration
bits : 3 - 8 (6 bit)
access : read-write

Enumeration:

7 : A7OUT2

Output is A7OUT2.

6 : A6OUT2

Output is A6OUT2.

5 : B3OUT2

Output is B3OUT2.

4 : B7OUT

Output is B7OUT.

3 : A6OUT

Output is A6OUT.

2 : B7OUT2

Output is B7OUT2

1 : ONE

Force output to 1.

0 : ZERO

Force output to 0

End of enumeration elements list.


INCFG

Counter/Timer Input Config
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INCFG INCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFGA0 CFGB0 CFGA1 CFGB1 CFGA2 CFGB2 CFGA3 CFGB3 CFGA4 CFGB4 CFGA5 CFGB5 CFGA6 CFGB6 CFGA7 CFGB7

CFGA0 : CTIMER A0 input configuration
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : CT1

Input is CT1

0 : CT0

Input is CT0

End of enumeration elements list.

CFGB0 : CTIMER B0 input configuration
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : CT3

Input is CT3

0 : CT2

Input is CT2

End of enumeration elements list.

CFGA1 : CTIMER A1 input configuration
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : CT5

Input is CT5

0 : CT4

Input is CT4

End of enumeration elements list.

CFGB1 : CTIMER B1 input configuration
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : CT7

Input is CT7

0 : CT6

Input is CT6

End of enumeration elements list.

CFGA2 : CTIMER A2 input configuration
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : CT9

Input is CT9

0 : CT8

Input is CT8

End of enumeration elements list.

CFGB2 : CTIMER B2 input configuration
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : CT11

Input is CT11

0 : CT10

Input is CT10

End of enumeration elements list.

CFGA3 : CTIMER A3 input configuration
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : CT13

Input is CT13

0 : CT12

Input is CT12

End of enumeration elements list.

CFGB3 : CTIMER B3 input configuration
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : CT15

Input is CT15

0 : CT14

Input is CT14

End of enumeration elements list.

CFGA4 : CTIMER A4 input configuration
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : CT17

Input is CT17

0 : CT16

Input is CT16

End of enumeration elements list.

CFGB4 : CTIMER B4 input configuration
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : CT19

Input is CT19

0 : CT18

Input is CT18

End of enumeration elements list.

CFGA5 : CTIMER A5 input configuration
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : CT21

Input is CT21

0 : CT20

Input is CT20

End of enumeration elements list.

CFGB5 : CTIMER B5 input configuration
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : CT23

Input is CT23

0 : CT22

Input is CT22

End of enumeration elements list.

CFGA6 : CTIMER A6 input configuration
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : CT25

Input is CT25

0 : CT24

Input is CT24

End of enumeration elements list.

CFGB6 : CTIMER B6 input configuration
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : CT27

Input is CT27

0 : CT26

Input is CT26

End of enumeration elements list.

CFGA7 : CTIMER A7 input configuration
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : CT29

Input is CT29

0 : CT28

Input is CT28

End of enumeration elements list.

CFGB7 : CTIMER B7 input configuration
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

1 : CT31

Input is CT31

0 : CT30

Input is CT30

End of enumeration elements list.


CMPRAUXA0

Counter/Timer A0 Compare Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA0 CMPRAUXA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A0 CMPR3A0

CMPR2A0 : Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A0 : Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


STCFG

Configuration Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCFG STCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL COMPARE_A_EN COMPARE_B_EN COMPARE_C_EN COMPARE_D_EN COMPARE_E_EN COMPARE_F_EN COMPARE_G_EN COMPARE_H_EN CLEAR FREEZE

CLKSEL : Selects an appropriate clock source and divider to use for the System Timer clock.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : NOCLK

No clock enabled.

1 : HFRC_DIV16

3MHz from the HFRC clock divider.

2 : HFRC_DIV256

187.5KHz from the HFRC clock divider.

3 : XTAL_DIV1

32768Hz from the crystal oscillator.

4 : XTAL_DIV2

16384Hz from the crystal oscillator.

5 : XTAL_DIV32

1024Hz from the crystal oscillator.

6 : LFRC_DIV1

Approximately 1KHz from the LFRC oscillator (uncalibrated).

7 : CTIMER0A

Use CTIMER 0 section A as a prescaler for the clock source.

8 : CTIMER0B

Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.

End of enumeration elements list.

COMPARE_A_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare A disabled.

1 : ENABLE

Compare A enabled.

End of enumeration elements list.

COMPARE_B_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare B disabled.

1 : ENABLE

Compare B enabled.

End of enumeration elements list.

COMPARE_C_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare C disabled.

1 : ENABLE

Compare C enabled.

End of enumeration elements list.

COMPARE_D_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare D disabled.

1 : ENABLE

Compare D enabled.

End of enumeration elements list.

COMPARE_E_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare E disabled.

1 : ENABLE

Compare E enabled.

End of enumeration elements list.

COMPARE_F_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare F disabled.

1 : ENABLE

Compare F enabled.

End of enumeration elements list.

COMPARE_G_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare G disabled.

1 : ENABLE

Compare G enabled.

End of enumeration elements list.

COMPARE_H_EN : Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met.
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : DISABLE

Compare H disabled.

1 : ENABLE

Compare H enabled.

End of enumeration elements list.

CLEAR : Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

0 : RUN

Let the COUNTER register run on its input clock.

1 : CLEAR

Stop the COUNTER register for loading.

End of enumeration elements list.

FREEZE : Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : THAW

Let the COUNTER register run on its input clock.

1 : FREEZE

Stop the COUNTER register for loading.

End of enumeration elements list.


STTMR

System Timer Count Register (Real Time Counter)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STTMR STTMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STTMR

STTMR : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write


CAPTURECONTROL

Capture Control Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPTURECONTROL CAPTURECONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTURE0 CAPTURE1 CAPTURE2 CAPTURE3

CAPTURE0 : Selects whether capture is enabled for the specified capture register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Capture function disabled.

1 : ENABLE

Capture function enabled.

End of enumeration elements list.

CAPTURE1 : Selects whether capture is enabled for the specified capture register.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : DISABLE

Capture function disabled.

1 : ENABLE

Capture function enabled.

End of enumeration elements list.

CAPTURE2 : Selects whether capture is enabled for the specified capture register.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : DISABLE

Capture function disabled.

1 : ENABLE

Capture function enabled.

End of enumeration elements list.

CAPTURE3 : Selects whether capture is enabled for the specified capture register.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : DISABLE

Capture function disabled.

1 : ENABLE

Capture function enabled.

End of enumeration elements list.


SCMPR0

Compare Register A
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR0 SCMPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR0

SCMPR0 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR1

Compare Register B
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR1 SCMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR1

SCMPR1 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR2

Compare Register C
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR2 SCMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR2

SCMPR2 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR3

Compare Register D
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR3 SCMPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR3

SCMPR3 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR4

Compare Register E
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR4 SCMPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR4

SCMPR4 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR5

Compare Register F
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR5 SCMPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR5

SCMPR5 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR6

Compare Register G
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR6 SCMPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR6

SCMPR6 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


SCMPR7

Compare Register H
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMPR7 SCMPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCMPR7

SCMPR7 : Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.
bits : 0 - 31 (32 bit)
access : read-write


CMPRAUXB0

Counter/Timer B0 Compare Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB0 CMPRAUXB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B0 CMPR3B0

CMPR2B0 : Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B0 : Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX0

Counter/Timer Auxiliary
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX0 AUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA0LMT TMRA0TRIG TMRA0NOSYNC TMRA0TINV TMRA0POL23 TMRA0EN23 TMRB0LMT TMRB0TRIG TMRB0NOSYNC TMRB0TINV TMRB0POL23 TMRB0EN23

TMRA0LMT : Counter/Timer A0 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA0TRIG : Counter/Timer A0 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B0OUT

Trigger source is CTIMERB0 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A1OUT

Trigger source is CTIMERA1 OUT.

5 : B1OUT

Trigger source is CTIMERB1 OUT.

6 : A5OUT

Trigger source is CTIMERA5 OUT.

7 : B5OUT

Trigger source is CTIMERB5 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : B6OUT2

Trigger source is CTIMERB6 OUT2.

11 : A2OUT2

Trigger source is CTIMERA2 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRA0NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA0TINV : Counter/Timer A0 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA0POL23 : Counter/Timer A0 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA0EN23 : Counter/Timer A0 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB0LMT : Counter/Timer B0 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB0TRIG : Counter/Timer B0 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A0OUT

Trigger source is CTIMERA0 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : B2OUT

Trigger source is CTIMERB2 OUT.

5 : B5OUT

Trigger source is CTIMERB5 OUT.

6 : A4OUT

Trigger source is CTIMERA4 OUT.

7 : B4OUT

Trigger source is CTIMERB4 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : B7OUT2

Trigger source is CTIMERB7 OUT2.

11 : A2OUT2

Trigger source is CTIMERA2 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B5OUT2DUAL

Trigger source is CTIMERB5 OUT2, dual edge.

15 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

End of enumeration elements list.

TMRB0NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB0TINV : Counter/Timer B0 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB0POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB0EN23 : Counter/Timer B0 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


SCAPT0

Capture Register A
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCAPT0 SCAPT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAPT0

SCAPT0 : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write


SCAPT1

Capture Register B
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCAPT1 SCAPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAPT1

SCAPT1 : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write


SCAPT2

Capture Register C
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCAPT2 SCAPT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAPT2

SCAPT2 : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write


SCAPT3

Capture Register D
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCAPT3 SCAPT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAPT3

SCAPT3 : Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.
bits : 0 - 31 (32 bit)
access : read-write


SNVR0

System Timer NVRAM_A Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNVR0 SNVR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNVR0

SNVR0 : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write


SNVR1

System Timer NVRAM_B Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNVR1 SNVR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNVR1

SNVR1 : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write


SNVR2

System Timer NVRAM_C Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNVR2 SNVR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNVR2

SNVR2 : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write


SNVR3

System Timer NVRAM_D Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNVR3 SNVR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNVR3

SNVR3 : Value of the 32-bit counter as it ticks over.
bits : 0 - 31 (32 bit)
access : read-write


TMR1

Counter/Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR1 TMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA1 CTTMRB1

CTTMRA1 : Counter/Timer A1.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB1 : Counter/Timer B1.
bits : 16 - 47 (32 bit)
access : read-write


INTEN

Counter/Timer Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTMRA0C0INT CTMRB0C0INT CTMRA1C0INT CTMRB1C0INT CTMRA2C0INT CTMRB2C0INT CTMRA3C0INT CTMRB3C0INT CTMRA4C0INT CTMRB4C0INT CTMRA5C0INT CTMRB5C0INT CTMRA6C0INT CTMRB6C0INT CTMRA7C0INT CTMRB7C0INT CTMRA0C1INT CTMRB0C1INT CTMRA1C1INT CTMRB1C1INT CTMRA2C1INT CTMRB2C1INT CTMRA3C1INT CTMRB3C1INT CTMRA4C1INT CTMRB4C1INT CTMRA5C1INT CTMRB5C1INT CTMRA6C1INT CTMRB6C1INT CTMRA7C1INT CTMRB7C1INT

CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write

CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write

CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write

CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write

CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write

CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write

CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write

CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write

CTMRA4C0INT : Counter/Timer A4 interrupt based on COMPR0.
bits : 8 - 16 (9 bit)
access : read-write

CTMRB4C0INT : Counter/Timer B4 interrupt based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

CTMRA5C0INT : Counter/Timer A5 interrupt based on COMPR0.
bits : 10 - 20 (11 bit)
access : read-write

CTMRB5C0INT : Counter/Timer B5 interrupt based on COMPR0.
bits : 11 - 22 (12 bit)
access : read-write

CTMRA6C0INT : Counter/Timer A6 interrupt based on COMPR0.
bits : 12 - 24 (13 bit)
access : read-write

CTMRB6C0INT : Counter/Timer B6 interrupt based on COMPR0.
bits : 13 - 26 (14 bit)
access : read-write

CTMRA7C0INT : Counter/Timer A7 interrupt based on COMPR0.
bits : 14 - 28 (15 bit)
access : read-write

CTMRB7C0INT : Counter/Timer B7 interrupt based on COMPR0.
bits : 15 - 30 (16 bit)
access : read-write

CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 16 - 32 (17 bit)
access : read-write

CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 17 - 34 (18 bit)
access : read-write

CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 18 - 36 (19 bit)
access : read-write

CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 19 - 38 (20 bit)
access : read-write

CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 20 - 40 (21 bit)
access : read-write

CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 21 - 42 (22 bit)
access : read-write

CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 22 - 44 (23 bit)
access : read-write

CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 23 - 46 (24 bit)
access : read-write

CTMRA4C1INT : Counter/Timer A4 interrupt based on COMPR1.
bits : 24 - 48 (25 bit)
access : read-write

CTMRB4C1INT : Counter/Timer B4 interrupt based on COMPR1.
bits : 25 - 50 (26 bit)
access : read-write

CTMRA5C1INT : Counter/Timer A5 interrupt based on COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

CTMRB5C1INT : Counter/Timer B5 interrupt based on COMPR1.
bits : 27 - 54 (28 bit)
access : read-write

CTMRA6C1INT : Counter/Timer A6 interrupt based on COMPR1.
bits : 28 - 56 (29 bit)
access : read-write

CTMRB6C1INT : Counter/Timer B6 interrupt based on COMPR1.
bits : 29 - 58 (30 bit)
access : read-write

CTMRA7C1INT : Counter/Timer A7 interrupt based on COMPR1.
bits : 30 - 60 (31 bit)
access : read-write

CTMRB7C1INT : Counter/Timer B7 interrupt based on COMPR1.
bits : 31 - 62 (32 bit)
access : read-write


INTSTAT

Counter/Timer Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTMRA0C0INT CTMRB0C0INT CTMRA1C0INT CTMRB1C0INT CTMRA2C0INT CTMRB2C0INT CTMRA3C0INT CTMRB3C0INT CTMRA4C0INT CTMRB4C0INT CTMRA5C0INT CTMRB5C0INT CTMRA6C0INT CTMRB6C0INT CTMRA7C0INT CTMRB7C0INT CTMRA0C1INT CTMRB0C1INT CTMRA1C1INT CTMRB1C1INT CTMRA2C1INT CTMRB2C1INT CTMRA3C1INT CTMRB3C1INT CTMRA4C1INT CTMRB4C1INT CTMRA5C1INT CTMRB5C1INT CTMRA6C1INT CTMRB6C1INT CTMRA7C1INT CTMRB7C1INT

CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write

CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write

CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write

CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write

CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write

CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write

CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write

CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write

CTMRA4C0INT : Counter/Timer A4 interrupt based on COMPR0.
bits : 8 - 16 (9 bit)
access : read-write

CTMRB4C0INT : Counter/Timer B4 interrupt based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

CTMRA5C0INT : Counter/Timer A5 interrupt based on COMPR0.
bits : 10 - 20 (11 bit)
access : read-write

CTMRB5C0INT : Counter/Timer B5 interrupt based on COMPR0.
bits : 11 - 22 (12 bit)
access : read-write

CTMRA6C0INT : Counter/Timer A6 interrupt based on COMPR0.
bits : 12 - 24 (13 bit)
access : read-write

CTMRB6C0INT : Counter/Timer B6 interrupt based on COMPR0.
bits : 13 - 26 (14 bit)
access : read-write

CTMRA7C0INT : Counter/Timer A7 interrupt based on COMPR0.
bits : 14 - 28 (15 bit)
access : read-write

CTMRB7C0INT : Counter/Timer B7 interrupt based on COMPR0.
bits : 15 - 30 (16 bit)
access : read-write

CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 16 - 32 (17 bit)
access : read-write

CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 17 - 34 (18 bit)
access : read-write

CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 18 - 36 (19 bit)
access : read-write

CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 19 - 38 (20 bit)
access : read-write

CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 20 - 40 (21 bit)
access : read-write

CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 21 - 42 (22 bit)
access : read-write

CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 22 - 44 (23 bit)
access : read-write

CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 23 - 46 (24 bit)
access : read-write

CTMRA4C1INT : Counter/Timer A4 interrupt based on COMPR1.
bits : 24 - 48 (25 bit)
access : read-write

CTMRB4C1INT : Counter/Timer B4 interrupt based on COMPR1.
bits : 25 - 50 (26 bit)
access : read-write

CTMRA5C1INT : Counter/Timer A5 interrupt based on COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

CTMRB5C1INT : Counter/Timer B5 interrupt based on COMPR1.
bits : 27 - 54 (28 bit)
access : read-write

CTMRA6C1INT : Counter/Timer A6 interrupt based on COMPR1.
bits : 28 - 56 (29 bit)
access : read-write

CTMRB6C1INT : Counter/Timer B6 interrupt based on COMPR1.
bits : 29 - 58 (30 bit)
access : read-write

CTMRA7C1INT : Counter/Timer A7 interrupt based on COMPR1.
bits : 30 - 60 (31 bit)
access : read-write

CTMRB7C1INT : Counter/Timer B7 interrupt based on COMPR1.
bits : 31 - 62 (32 bit)
access : read-write


INTCLR

Counter/Timer Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTMRA0C0INT CTMRB0C0INT CTMRA1C0INT CTMRB1C0INT CTMRA2C0INT CTMRB2C0INT CTMRA3C0INT CTMRB3C0INT CTMRA4C0INT CTMRB4C0INT CTMRA5C0INT CTMRB5C0INT CTMRA6C0INT CTMRB6C0INT CTMRA7C0INT CTMRB7C0INT CTMRA0C1INT CTMRB0C1INT CTMRA1C1INT CTMRB1C1INT CTMRA2C1INT CTMRB2C1INT CTMRA3C1INT CTMRB3C1INT CTMRA4C1INT CTMRB4C1INT CTMRA5C1INT CTMRB5C1INT CTMRA6C1INT CTMRB6C1INT CTMRA7C1INT CTMRB7C1INT

CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write

CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write

CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write

CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write

CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write

CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write

CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write

CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write

CTMRA4C0INT : Counter/Timer A4 interrupt based on COMPR0.
bits : 8 - 16 (9 bit)
access : read-write

CTMRB4C0INT : Counter/Timer B4 interrupt based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

CTMRA5C0INT : Counter/Timer A5 interrupt based on COMPR0.
bits : 10 - 20 (11 bit)
access : read-write

CTMRB5C0INT : Counter/Timer B5 interrupt based on COMPR0.
bits : 11 - 22 (12 bit)
access : read-write

CTMRA6C0INT : Counter/Timer A6 interrupt based on COMPR0.
bits : 12 - 24 (13 bit)
access : read-write

CTMRB6C0INT : Counter/Timer B6 interrupt based on COMPR0.
bits : 13 - 26 (14 bit)
access : read-write

CTMRA7C0INT : Counter/Timer A7 interrupt based on COMPR0.
bits : 14 - 28 (15 bit)
access : read-write

CTMRB7C0INT : Counter/Timer B7 interrupt based on COMPR0.
bits : 15 - 30 (16 bit)
access : read-write

CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 16 - 32 (17 bit)
access : read-write

CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 17 - 34 (18 bit)
access : read-write

CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 18 - 36 (19 bit)
access : read-write

CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 19 - 38 (20 bit)
access : read-write

CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 20 - 40 (21 bit)
access : read-write

CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 21 - 42 (22 bit)
access : read-write

CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 22 - 44 (23 bit)
access : read-write

CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 23 - 46 (24 bit)
access : read-write

CTMRA4C1INT : Counter/Timer A4 interrupt based on COMPR1.
bits : 24 - 48 (25 bit)
access : read-write

CTMRB4C1INT : Counter/Timer B4 interrupt based on COMPR1.
bits : 25 - 50 (26 bit)
access : read-write

CTMRA5C1INT : Counter/Timer A5 interrupt based on COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

CTMRB5C1INT : Counter/Timer B5 interrupt based on COMPR1.
bits : 27 - 54 (28 bit)
access : read-write

CTMRA6C1INT : Counter/Timer A6 interrupt based on COMPR1.
bits : 28 - 56 (29 bit)
access : read-write

CTMRB6C1INT : Counter/Timer B6 interrupt based on COMPR1.
bits : 29 - 58 (30 bit)
access : read-write

CTMRA7C1INT : Counter/Timer A7 interrupt based on COMPR1.
bits : 30 - 60 (31 bit)
access : read-write

CTMRB7C1INT : Counter/Timer B7 interrupt based on COMPR1.
bits : 31 - 62 (32 bit)
access : read-write


INTSET

Counter/Timer Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTMRA0C0INT CTMRB0C0INT CTMRA1C0INT CTMRB1C0INT CTMRA2C0INT CTMRB2C0INT CTMRA3C0INT CTMRB3C0INT CTMRA4C0INT CTMRB4C0INT CTMRA5C0INT CTMRB5C0INT CTMRA6C0INT CTMRB6C0INT CTMRA7C0INT CTMRB7C0INT CTMRA0C1INT CTMRB0C1INT CTMRA1C1INT CTMRB1C1INT CTMRA2C1INT CTMRB2C1INT CTMRA3C1INT CTMRB3C1INT CTMRA4C1INT CTMRB4C1INT CTMRA5C1INT CTMRB5C1INT CTMRA6C1INT CTMRB6C1INT CTMRA7C1INT CTMRB7C1INT

CTMRA0C0INT : Counter/Timer A0 interrupt based on COMPR0.
bits : 0 - 0 (1 bit)
access : read-write

CTMRB0C0INT : Counter/Timer B0 interrupt based on COMPR0.
bits : 1 - 2 (2 bit)
access : read-write

CTMRA1C0INT : Counter/Timer A1 interrupt based on COMPR0.
bits : 2 - 4 (3 bit)
access : read-write

CTMRB1C0INT : Counter/Timer B1 interrupt based on COMPR0.
bits : 3 - 6 (4 bit)
access : read-write

CTMRA2C0INT : Counter/Timer A2 interrupt based on COMPR0.
bits : 4 - 8 (5 bit)
access : read-write

CTMRB2C0INT : Counter/Timer B2 interrupt based on COMPR0.
bits : 5 - 10 (6 bit)
access : read-write

CTMRA3C0INT : Counter/Timer A3 interrupt based on COMPR0.
bits : 6 - 12 (7 bit)
access : read-write

CTMRB3C0INT : Counter/Timer B3 interrupt based on COMPR0.
bits : 7 - 14 (8 bit)
access : read-write

CTMRA4C0INT : Counter/Timer A4 interrupt based on COMPR0.
bits : 8 - 16 (9 bit)
access : read-write

CTMRB4C0INT : Counter/Timer B4 interrupt based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

CTMRA5C0INT : Counter/Timer A5 interrupt based on COMPR0.
bits : 10 - 20 (11 bit)
access : read-write

CTMRB5C0INT : Counter/Timer B5 interrupt based on COMPR0.
bits : 11 - 22 (12 bit)
access : read-write

CTMRA6C0INT : Counter/Timer A6 interrupt based on COMPR0.
bits : 12 - 24 (13 bit)
access : read-write

CTMRB6C0INT : Counter/Timer B6 interrupt based on COMPR0.
bits : 13 - 26 (14 bit)
access : read-write

CTMRA7C0INT : Counter/Timer A7 interrupt based on COMPR0.
bits : 14 - 28 (15 bit)
access : read-write

CTMRB7C0INT : Counter/Timer B7 interrupt based on COMPR0.
bits : 15 - 30 (16 bit)
access : read-write

CTMRA0C1INT : Counter/Timer A0 interrupt based on COMPR1.
bits : 16 - 32 (17 bit)
access : read-write

CTMRB0C1INT : Counter/Timer B0 interrupt based on COMPR1.
bits : 17 - 34 (18 bit)
access : read-write

CTMRA1C1INT : Counter/Timer A1 interrupt based on COMPR1.
bits : 18 - 36 (19 bit)
access : read-write

CTMRB1C1INT : Counter/Timer B1 interrupt based on COMPR1.
bits : 19 - 38 (20 bit)
access : read-write

CTMRA2C1INT : Counter/Timer A2 interrupt based on COMPR1.
bits : 20 - 40 (21 bit)
access : read-write

CTMRB2C1INT : Counter/Timer B2 interrupt based on COMPR1.
bits : 21 - 42 (22 bit)
access : read-write

CTMRA3C1INT : Counter/Timer A3 interrupt based on COMPR1.
bits : 22 - 44 (23 bit)
access : read-write

CTMRB3C1INT : Counter/Timer B3 interrupt based on COMPR1.
bits : 23 - 46 (24 bit)
access : read-write

CTMRA4C1INT : Counter/Timer A4 interrupt based on COMPR1.
bits : 24 - 48 (25 bit)
access : read-write

CTMRB4C1INT : Counter/Timer B4 interrupt based on COMPR1.
bits : 25 - 50 (26 bit)
access : read-write

CTMRA5C1INT : Counter/Timer A5 interrupt based on COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

CTMRB5C1INT : Counter/Timer B5 interrupt based on COMPR1.
bits : 27 - 54 (28 bit)
access : read-write

CTMRA6C1INT : Counter/Timer A6 interrupt based on COMPR1.
bits : 28 - 56 (29 bit)
access : read-write

CTMRB6C1INT : Counter/Timer B6 interrupt based on COMPR1.
bits : 29 - 58 (30 bit)
access : read-write

CTMRA7C1INT : Counter/Timer A7 interrupt based on COMPR1.
bits : 30 - 60 (31 bit)
access : read-write

CTMRB7C1INT : Counter/Timer B7 interrupt based on COMPR1.
bits : 31 - 62 (32 bit)
access : read-write


CMPRA1

Counter/Timer A1 Compare Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA1 CMPRA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A1 CMPR1A1

CMPR0A1 : Counter/Timer A1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A1 : Counter/Timer A1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB1

Counter/Timer B1 Compare Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB1 CMPRB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B1 CMPR1B1

CMPR0B1 : Counter/Timer B1 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B1 : Counter/Timer B1 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL1

Counter/Timer Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA1EN TMRA1CLK TMRA1FN TMRA1IE0 TMRA1IE1 TMRA1CLR TMRA1POL TMRB1EN TMRB1CLK TMRB1FN TMRB1IE0 TMRB1IE1 TMRB1CLR TMRB1POL CTLINK1

TMRA1EN : Counter/Timer A1 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A1 Disable.

1 : EN

Counter/Timer A1 Enable.

End of enumeration elements list.

TMRA1CLK : Counter/Timer A1 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB1

Clock source is CTIMERB1 OUT.

21 : CTMRA0

Clock source is CTIMERA0 OUT.

22 : CTMRB0

Clock source is CTIMERB0 OUT.

23 : CTMRA2

Clock source is CTIMERA2 OUT.

24 : CTMRB2

Clock source is CTIMERB2 OUT.

25 : CTMRB3

Clock source is CTIMERB3 OUT.

26 : CTMRB4

Clock source is CTIMERB4 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA1FN : Counter/Timer A1 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A1, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA1IE0 : Counter/Timer A1 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A1 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A1 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA1IE1 : Counter/Timer A1 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A1 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A1 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA1CLR : Counter/Timer A1 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A1 to run

1 : CLEAR

Holds counter/timer A1 at 0x0000.

End of enumeration elements list.

TMRA1POL : Counter/Timer A1 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA1 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA1 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB1EN : Counter/Timer B1 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B1 Disable.

1 : EN

Counter/Timer B1 Enable.

End of enumeration elements list.

TMRB1CLK : Counter/Timer B1 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA1

Clock source is CTIMERA1 OUT.

21 : CTMRA0

Clock source is CTIMERA0 OUT.

22 : CTMRB0

Clock source is CTIMERB0 OUT.

23 : CTMRA2

Clock source is CTIMERA2 OUT.

24 : CTMRB2

Clock source is CTIMERB2 OUT.

25 : CTMRB3

Clock source is CTIMERB3 OUT.

26 : CTMRB4

Clock source is CTIMERB4 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB1FN : Counter/Timer B1 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B1, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB1IE0 : Counter/Timer B1 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B1 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B1 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB1IE1 : Counter/Timer B1 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B1 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B1 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB1CLR : Counter/Timer B1 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B1 to run

1 : CLEAR

Holds counter/timer B1 at 0x0000.

End of enumeration elements list.

TMRB1POL : Counter/Timer B1 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB1 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB1 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK1 : Counter/Timer A1/B1 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A1/B1 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A1/B1 timers into a single 32-bit timer.

End of enumeration elements list.


STMINTEN

STIMER Interrupt registers: Enable
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STMINTEN STMINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPAREA COMPAREB COMPAREC COMPARED COMPAREE COMPAREF COMPAREG COMPAREH OVERFLOW CAPTUREA CAPTUREB CAPTUREC CAPTURED

COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : OFLOW_INT

Overflow interrupt status bit was set.

End of enumeration elements list.

CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : CAPA_INT

CAPTURE A interrupt status bit was set.

End of enumeration elements list.

CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : CAPB_INT

CAPTURE B interrupt status bit was set.

End of enumeration elements list.

CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : CAPC_INT

CAPTURE C interrupt status bit was set.

End of enumeration elements list.

CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : CAPD_INT

Capture D interrupt status bit was set.

End of enumeration elements list.


STMINTSTAT

STIMER Interrupt registers: Status
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STMINTSTAT STMINTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPAREA COMPAREB COMPAREC COMPARED COMPAREE COMPAREF COMPAREG COMPAREH OVERFLOW CAPTUREA CAPTUREB CAPTUREC CAPTURED

COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : OFLOW_INT

Overflow interrupt status bit was set.

End of enumeration elements list.

CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : CAPA_INT

CAPTURE A interrupt status bit was set.

End of enumeration elements list.

CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : CAPB_INT

CAPTURE B interrupt status bit was set.

End of enumeration elements list.

CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : CAPC_INT

CAPTURE C interrupt status bit was set.

End of enumeration elements list.

CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : CAPD_INT

Capture D interrupt status bit was set.

End of enumeration elements list.


STMINTCLR

STIMER Interrupt registers: Clear
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STMINTCLR STMINTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPAREA COMPAREB COMPAREC COMPARED COMPAREE COMPAREF COMPAREG COMPAREH OVERFLOW CAPTUREA CAPTUREB CAPTUREC CAPTURED

COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : OFLOW_INT

Overflow interrupt status bit was set.

End of enumeration elements list.

CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : CAPA_INT

CAPTURE A interrupt status bit was set.

End of enumeration elements list.

CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : CAPB_INT

CAPTURE B interrupt status bit was set.

End of enumeration elements list.

CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : CAPC_INT

CAPTURE C interrupt status bit was set.

End of enumeration elements list.

CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : CAPD_INT

Capture D interrupt status bit was set.

End of enumeration elements list.


STMINTSET

STIMER Interrupt registers: Set
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STMINTSET STMINTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPAREA COMPAREB COMPAREC COMPARED COMPAREE COMPAREF COMPAREG COMPAREH OVERFLOW CAPTUREA CAPTUREB CAPTUREC CAPTURED

COMPAREA : COUNTER is greater than or equal to COMPARE register A.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREB : COUNTER is greater than or equal to COMPARE register B.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREC : COUNTER is greater than or equal to COMPARE register C.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPARED : COUNTER is greater than or equal to COMPARE register D.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREE : COUNTER is greater than or equal to COMPARE register E.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREF : COUNTER is greater than or equal to COMPARE register F.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREG : COUNTER is greater than or equal to COMPARE register G.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

COMPAREH : COUNTER is greater than or equal to COMPARE register H.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : COMPARED

COUNTER greater than or equal to COMPARE register.

End of enumeration elements list.

OVERFLOW : COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : OFLOW_INT

Overflow interrupt status bit was set.

End of enumeration elements list.

CAPTUREA : CAPTURE register A has grabbed the value in the counter
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : CAPA_INT

CAPTURE A interrupt status bit was set.

End of enumeration elements list.

CAPTUREB : CAPTURE register B has grabbed the value in the counter
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : CAPB_INT

CAPTURE B interrupt status bit was set.

End of enumeration elements list.

CAPTUREC : CAPTURE register C has grabbed the value in the counter
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : CAPC_INT

CAPTURE C interrupt status bit was set.

End of enumeration elements list.

CAPTURED : CAPTURE register D has grabbed the value in the counter
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : CAPD_INT

Capture D interrupt status bit was set.

End of enumeration elements list.


CMPRAUXA1

Counter/Timer A1 Compare Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA1 CMPRAUXA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A1 CMPR3A1

CMPR2A1 : Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A1 : Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB1

Counter/Timer B1 Compare Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB1 CMPRAUXB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B1 CMPR3B1

CMPR2B1 : Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B1 : Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX1

Counter/Timer Auxiliary
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX1 AUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA1LMT TMRA1TRIG TMRA1NOSYNC TMRA1TINV TMRA1POL23 TMRA1EN23 TMRB1LMT TMRB1TRIG TMRB1NOSYNC TMRB1TINV TMRB1POL23 TMRB1EN23

TMRA1LMT : Counter/Timer A1 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA1TRIG : Counter/Timer A1 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B1OUT

Trigger source is CTIMERB1 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A0OUT

Trigger source is CTIMERA0 OUT.

5 : B0OUT

Trigger source is CTIMERB0 OUT.

6 : A5OUT

Trigger source is CTIMERA5 OUT.

7 : B5OUT

Trigger source is CTIMERB5 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A4OUT2

Trigger source is CTIMERA4 OUT2.

11 : B4OUT2

Trigger source is CTIMERB4 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B5OUT2DUAL

Trigger source is CTIMERB5 OUT2, dual edge.

15 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

End of enumeration elements list.

TMRA1NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA1TINV : Counter/Timer A1 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA1POL23 : Counter/Timer A1 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORMAL

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA1EN23 : Counter/Timer A1 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB1LMT : Counter/Timer B1 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB1TRIG : Counter/Timer B1 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A1OUT

Trigger source is CTIMERA1 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A6OUT

Trigger source is CTIMERA6 OUT.

5 : B6OUT

Trigger source is CTIMERB6 OUT.

6 : A0OUT

Trigger source is CTIMERA0 OUT.

7 : B0OUT

Trigger source is CTIMERB0 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A4OUT2

Trigger source is CTIMERA4 OUT2.

11 : B4OUT2

Trigger source is CTIMERB4 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B5OUT2DUAL

Trigger source is CTIMERB5 OUT2, dual edge.

15 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

End of enumeration elements list.

TMRB1NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB1TINV : Counter/Timer B1 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB1POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB1EN23 : Counter/Timer B1 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


CMPRA0

Counter/Timer A0 Compare Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA0 CMPRA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A0 CMPR1A0

CMPR0A0 : Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A0 : Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


TMR2

Counter/Timer Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR2 TMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA2 CTTMRB2

CTTMRA2 : Counter/Timer A2.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB2 : Counter/Timer B2.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA2

Counter/Timer A2 Compare Registers
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA2 CMPRA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A2 CMPR1A2

CMPR0A2 : Counter/Timer A2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A2 : Counter/Timer A2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB2

Counter/Timer B2 Compare Registers
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB2 CMPRB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B2 CMPR1B2

CMPR0B2 : Counter/Timer B2 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B2 : Counter/Timer B2 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL2

Counter/Timer Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA2EN TMRA2CLK TMRA2FN TMRA2IE0 TMRA2IE1 TMRA2CLR TMRA2POL TMRB2EN TMRB2CLK TMRB2FN TMRB2IE0 TMRB2IE1 TMRB2CLR TMRB2POL CTLINK2

TMRA2EN : Counter/Timer A2 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A2 Disable.

1 : EN

Counter/Timer A2 Enable.

End of enumeration elements list.

TMRA2CLK : Counter/Timer A2 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB2

Clock source is CTIMERB2 OUT.

21 : CTMRB3

Clock source is CTIMERA3 OUT.

22 : CTMRA3

Clock source is CTIMERB3 OUT.

23 : CTMRA4

Clock source is CTIMERA4 OUT.

24 : CTMRB4

Clock source is CTIMERB4 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA2FN : Counter/Timer A2 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A2, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA2IE0 : Counter/Timer A2 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A2 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A2 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA2IE1 : Counter/Timer A2 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A2 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A2 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA2CLR : Counter/Timer A2 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A2 to run

1 : CLEAR

Holds counter/timer A2 at 0x0000.

End of enumeration elements list.

TMRA2POL : Counter/Timer A2 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA2 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA2 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB2EN : Counter/Timer B2 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B2 Disable.

1 : EN

Counter/Timer B2 Enable.

End of enumeration elements list.

TMRB2CLK : Counter/Timer B2 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA2

Clock source is CTIMERA2 OUT.

21 : CTMRB3

Clock source is CTIMERA3 OUT.

22 : CTMRA3

Clock source is CTIMERB3 OUT.

23 : CTMRA4

Clock source is CTIMERA4 OUT.

24 : CTMRB4

Clock source is CTIMERB4 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB2FN : Counter/Timer B2 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B2, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB2IE0 : Counter/Timer B2 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B2 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B2 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB2IE1 : Counter/Timer B2 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B2 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B2 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB2CLR : Counter/Timer B2 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B2 to run

1 : CLEAR

Holds counter/timer B2 at 0x0000.

End of enumeration elements list.

TMRB2POL : Counter/Timer B2 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB2 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB2 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK2 : Counter/Timer A2/B2 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A2/B2 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A2/B2 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA2

Counter/Timer A2 Compare Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA2 CMPRAUXA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A2 CMPR3A2

CMPR2A2 : Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A2 : Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB2

Counter/Timer B2 Compare Registers
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB2 CMPRAUXB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B2 CMPR3B2

CMPR2B2 : Counter/Timer B2 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B2 : Counter/Timer B2 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX2

Counter/Timer Auxiliary
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX2 AUX2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA2LMT TMRA2TRIG TMRA2NOSYNC TMRA2TINV TMRA2POL23 TMRA2EN23 TMRB2LMT TMRB2TRIG TMRB2NOSYNC TMRB2TINV TMRB2POL23 TMRB2EN23

TMRA2LMT : Counter/Timer A2 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA2TRIG : Counter/Timer A2 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B2OUT

Trigger source is CTIMERB2 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A0OUT

Trigger source is CTIMERA0 OUT.

5 : B0OUT

Trigger source is CTIMERB0 OUT.

6 : A4OUT

Trigger source is CTIMERA4 OUT.

7 : B4OUT

Trigger source is CTIMERB4 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A5OUT2

Trigger source is CTIMERA5 OUT2.

11 : B5OUT2

Trigger source is CTIMERB5 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRA2NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA2TINV : Counter/Timer A2 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA2POL23 : Counter/Timer A2 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA2EN23 : Counter/Timer A2 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB2LMT : Counter/Timer B2 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB2TRIG : Counter/Timer B2 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A2OUT

Trigger source is CTIMERA2 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A1OUT

Trigger source is CTIMERA1 OUT.

5 : B1OUT

Trigger source is CTIMERB1 OUT.

6 : A4OUT

Trigger source is CTIMERA4 OUT.

7 : B4OUT

Trigger source is CTIMERB4 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A5OUT2

Trigger source is CTIMERA5 OUT2.

11 : B5OUT2

Trigger source is CTIMERB5 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRB2NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB2TINV : Counter/Timer B2 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB2POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB2EN23 : Counter/Timer B2 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


TMR3

Counter/Timer Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR3 TMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA3 CTTMRB3

CTTMRA3 : Counter/Timer A3.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB3 : Counter/Timer B3.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA3

Counter/Timer A3 Compare Registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA3 CMPRA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A3 CMPR1A3

CMPR0A3 : Counter/Timer A3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A3 : Counter/Timer A3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB3

Counter/Timer B3 Compare Registers
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB3 CMPRB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B3 CMPR1B3

CMPR0B3 : Counter/Timer B3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B3 : Counter/Timer B3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL3

Counter/Timer Control
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA3EN TMRA3CLK TMRA3FN TMRA3IE0 TMRA3IE1 TMRA3CLR TMRA3POL ADCEN TMRB3EN TMRB3CLK TMRB3FN TMRB3IE0 TMRB3IE1 TMRB3CLR TMRB3POL CTLINK3

TMRA3EN : Counter/Timer A3 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A3 Disable.

1 : EN

Counter/Timer A3 Enable.

End of enumeration elements list.

TMRA3CLK : Counter/Timer A3 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB3

Clock source is CTIMERB3 OUT.

21 : CTMRA2

Clock source is CTIMERA2 OUT.

22 : CTMRB2

Clock source is CTIMERB2 OUT.

23 : CTMRA4

Clock source is CTIMERA4 OUT.

24 : CTMRB4

Clock source is CTIMERB4 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA3FN : Counter/Timer A3 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A3, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA3IE0 : Counter/Timer A3 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A3 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A3 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA3IE1 : Counter/Timer A3 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A3 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A3 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA3CLR : Counter/Timer A3 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A3 to run

1 : CLEAR

Holds counter/timer A3 at 0x0000.

End of enumeration elements list.

TMRA3POL : Counter/Timer A3 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA3 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA3 pin is the inverse of the timer output.

End of enumeration elements list.

ADCEN : Special Timer A3 enable for ADC function.
bits : 15 - 30 (16 bit)
access : read-write

TMRB3EN : Counter/Timer B3 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B3 Disable.

1 : EN

Counter/Timer B3 Enable.

End of enumeration elements list.

TMRB3CLK : Counter/Timer B3 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA3

Clock source is CTIMERA3 OUT.

21 : CTMRA2

Clock source is CTIMERA2 OUT.

22 : CTMRB2

Clock source is CTIMERB2 OUT.

23 : CTMRA4

Clock source is CTIMERA4 OUT.

24 : CTMRB4

Clock source is CTIMERB4 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB3FN : Counter/Timer B3 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B3, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB3IE0 : Counter/Timer B3 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B3 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B3 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB3IE1 : Counter/Timer B3 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B3 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B3 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB3CLR : Counter/Timer B3 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B3 to run

1 : CLEAR

Holds counter/timer B3 at 0x0000.

End of enumeration elements list.

TMRB3POL : Counter/Timer B3 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB3 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB3 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK3 : Counter/Timer A3/B3 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A3/B3 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A3/B3 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA3

Counter/Timer A3 Compare Registers
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA3 CMPRAUXA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A3 CMPR3A3

CMPR2A3 : Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A3 : Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB3

Counter/Timer B3 Compare Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB3 CMPRAUXB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B3 CMPR3B3

CMPR2B3 : Counter/Timer B3 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B3 : Counter/Timer B3 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX3

Counter/Timer Auxiliary
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX3 AUX3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA3LMT TMRA3TRIG TMRA3NOSYNC TMRA3TINV TMRA3POL23 TMRA3EN23 TMRB3LMT TMRB3TRIG TMRB3NOSYNC TMRB3TINV TMRB3POL23 TMRB3EN23

TMRA3LMT : Counter/Timer A3 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA3TRIG : Counter/Timer A3 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B3OUT

Trigger source is CTIMERB3 OUT.

2 : B2OUT

Trigger source is CTIMERB2 OUT.

3 : A2OUT

Trigger source is CTIMERA2 OUT.

4 : A4OUT

Trigger source is CTIMERA4 OUT.

5 : B4OUT

Trigger source is CTIMERB4 OUT.

6 : A7OUT

Trigger source is CTIMERA7 OUT.

7 : B7OUT

Trigger source is CTIMERB7 OUT.

8 : B5OUT2

Trigger source is CTIMERB5 OUT2.

9 : A5OUT2

Trigger source is CTIMERA5 OUT2.

10 : A1OUT2

Trigger source is CTIMERA1 OUT2.

11 : B1OUT2

Trigger source is CTIMERB1 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B2OUT2DUAL

Trigger source is CTIMERB2 OUT2, dual edge.

15 : A2OUT2DUAL

Trigger source is CTIMERA2 OUT2, dual edge.

End of enumeration elements list.

TMRA3NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA3TINV : Counter/Timer A3 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA3POL23 : Counter/Timer A3 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA3EN23 : Counter/Timer A3 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB3LMT : Counter/Timer B3 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB3TRIG : Counter/Timer B3 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A3OUT

Trigger source is CTIMERA3 OUT.

2 : B2OUT

Trigger source is CTIMERB2 OUT.

3 : A2OUT

Trigger source is CTIMERA2 OUT.

4 : A4OUT

Trigger source is CTIMERA4 OUT.

5 : B4OUT

Trigger source is CTIMERB4 OUT.

6 : A6OUT

Trigger source is CTIMERA6 OUT.

7 : B6OUT

Trigger source is CTIMERB6 OUT.

8 : B5OUT2

Trigger source is CTIMERB5 OUT2.

9 : A5OUT2

Trigger source is CTIMERA5 OUT2.

10 : A1OUT2

Trigger source is CTIMERA1 OUT2.

11 : B1OUT2

Trigger source is CTIMERB1 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B2OUT2DUAL

Trigger source is CTIMERB2 OUT2, dual edge.

15 : A2OUT2DUAL

Trigger source is CTIMERA2 OUT2, dual edge.

End of enumeration elements list.

TMRB3NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB3TINV : Counter/Timer B3 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB3POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB3EN23 : Counter/Timer B3 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


CMPRB0

Counter/Timer B0 Compare Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB0 CMPRB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B0 CMPR1B0

CMPR0B0 : Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B0 : Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


TMR4

Counter/Timer Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR4 TMR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA4 CTTMRB4

CTTMRA4 : Counter/Timer A4.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB4 : Counter/Timer B4.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA4

Counter/Timer A4 Compare Registers
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA4 CMPRA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A4 CMPR1A4

CMPR0A4 : Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A4 : Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB4

Counter/Timer B4 Compare Registers
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB4 CMPRB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B4 CMPR1B4

CMPR0B4 : Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B4 : Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


CTRL4

Counter/Timer Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL4 CTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA4EN TMRA4CLK TMRA4FN TMRA4IE0 TMRA4IE1 TMRA4CLR TMRA4POL TMRB4EN TMRB4CLK TMRB4FN TMRB4IE0 TMRB4IE1 TMRB4CLR TMRB4POL CTLINK4

TMRA4EN : Counter/Timer A4 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A4 Disable.

1 : EN

Counter/Timer A4 Enable.

End of enumeration elements list.

TMRA4CLK : Counter/Timer A4 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4. (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB4

Clock source is CTIMERB4 OUT.

21 : CTMRA1

Clock source is CTIMERA1 OUT.

22 : CTMRB1

Clock source is CTIMERB1 OUT.

23 : CTMRA5

Clock source is CTIMERA5 OUT.

24 : CTMRB5

Clock source is CTIMERB5 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB2

Clock source is CTIMERB2 OUT.

27 : CTMRB3

Clock source is CTIMERB3 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA4FN : Counter/Timer A4 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A4, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A4, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A4, assert, count to CMPR1A4, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A4, assert, count to CMPR1A4, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA4IE0 : Counter/Timer A4 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A4 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A4 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA4IE1 : Counter/Timer A4 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A4 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A4 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA4CLR : Counter/Timer A4 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A4 to run

1 : CLEAR

Holds counter/timer A4 at 0x0000.

End of enumeration elements list.

TMRA4POL : Counter/Timer A4 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA4 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA4 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB4EN : Counter/Timer B4 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B4 Disable.

1 : EN

Counter/Timer B4 Enable.

End of enumeration elements list.

TMRB4CLK : Counter/Timer B4 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA4

Clock source is CTIMERA4 OUT.

21 : CTMRA1

Clock source is CTIMERA1 OUT.

22 : CTMRB1

Clock source is CTIMERB1 OUT.

23 : CTMRA5

Clock source is CTIMERA5 OUT.

24 : CTMRB5

Clock source is CTIMERB5 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB2

Clock source is CTIMERB2 OUT.

27 : CTMRB3

Clock source is CTIMERB3 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB4FN : Counter/Timer B4 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B4, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B4, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B4, assert, count to CMPR1B4, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B4, assert, count to CMPR1B4, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB4IE0 : Counter/Timer B4 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B4 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B4 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB4IE1 : Counter/Timer B4 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B4 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B4 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB4CLR : Counter/Timer B4 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B4 to run

1 : CLEAR

Holds counter/timer B4 at 0x0000.

End of enumeration elements list.

TMRB4POL : Counter/Timer B4 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB4 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB4 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK4 : Counter/Timer A4/B4 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A4/B4 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A4/B4 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA4

Counter/Timer A4 Compare Registers
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA4 CMPRAUXA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A4 CMPR3A4

CMPR2A4 : Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A4 : Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB4

Counter/Timer B4 Compare Registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB4 CMPRAUXB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B4 CMPR3B4

CMPR2B4 : Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B4 : Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX4

Counter/Timer Auxiliary
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX4 AUX4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA4LMT TMRA4TRIG TMRA4NOSYNC TMRA4TINV TMRA4POL23 TMRA4EN23 TMRB4LMT TMRB4TRIG TMRB4NOSYNC TMRB4TINV TMRB4POL23 TMRB4EN23

TMRA4LMT : Counter/Timer A4 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA4TRIG : Counter/Timer A4 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : STIMER

Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER interrupt

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A6OUT

Trigger source is CTIMERA6 OUT.

5 : B6OUT

Trigger source is CTIMERB6 OUT.

6 : A2OUT

Trigger source is CTIMERA2 OUT.

7 : B2OUT

Trigger source is CTIMERB2 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A1OUT2

Trigger source is CTIMERA1 OUT2.

11 : B1OUT2

Trigger source is CTIMERB1 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B5OUT2DUAL

Trigger source is CTIMERB5 OUT2, dual edge.

15 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

End of enumeration elements list.

TMRA4NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA4TINV : Counter/Timer A4 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA4POL23 : Counter/Timer A4 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA4EN23 : Counter/Timer A4 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB4LMT : Counter/Timer B4 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB4TRIG : Counter/Timer B4 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A4OUT

Trigger source is CTIMERA4 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A7OUT

Trigger source is CTIMERA7 OUT.

5 : B7OUT

Trigger source is CTIMERB7 OUT.

6 : A1OUT

Trigger source is CTIMERA1 OUT.

7 : B1OUT

Trigger source is CTIMERB1 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A1OUT2

Trigger source is CTIMERA1 OUT2.

11 : B1OUT2

Trigger source is CTIMERB1 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B5OUT2DUAL

Trigger source is CTIMERB5 OUT2, dual edge.

15 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

End of enumeration elements list.

TMRB4NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB4TINV : Counter/Timer B4 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB4POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB4EN23 : Counter/Timer B4 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


TMR5

Counter/Timer Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR5 TMR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA5 CTTMRB5

CTTMRA5 : Counter/Timer A5.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB5 : Counter/Timer B5.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA5

Counter/Timer A5 Compare Registers
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA5 CMPRA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A5 CMPR1A5

CMPR0A5 : Counter/Timer A5 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A5 : Counter/Timer A5 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB5

Counter/Timer B5 Compare Registers
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB5 CMPRB5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B5 CMPR1B5

CMPR0B5 : Counter/Timer B5 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B5 : Counter/Timer B5 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL5

Counter/Timer Control
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL5 CTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA5EN TMRA5CLK TMRA5FN TMRA5IE0 TMRA5IE1 TMRA5CLR TMRA5POL TMRB5EN TMRB5CLK TMRB5FN TMRB5IE0 TMRB5IE1 TMRB5CLR TMRB5POL CTLINK5

TMRA5EN : Counter/Timer A5 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A5 Disable.

1 : EN

Counter/Timer A5 Enable.

End of enumeration elements list.

TMRA5CLK : Counter/Timer A5 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB5

Clock source is CTIMERB5 OUT.

21 : CTMRA0

Clock source is CTIMERA0 OUT.

22 : CTMRB0

Clock source is CTIMERB0 OUT.

23 : CTMRA6

Clock source is CTIMERA6 OUT.

24 : CTMRB6

Clock source is CTIMERB6 OUT.

25 : CTMRB1

Clock source is CTIMERB1 OUT.

26 : CTMRB2

Clock source is CTIMERB2 OUT.

27 : CTMRB3

Clock source is CTIMERB3 OUT.

28 : CTMRB4

Clock source is CTIMERB4 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA5FN : Counter/Timer A5 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A5, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A5, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A5, assert, count to CMPR1A5, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A5, assert, count to CMPR1A5, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA5IE0 : Counter/Timer A5 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A5 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A5 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA5IE1 : Counter/Timer A5 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A5 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A5 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA5CLR : Counter/Timer A5 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A5 to run

1 : CLEAR

Holds counter/timer A5 at 0x0000.

End of enumeration elements list.

TMRA5POL : Counter/Timer A5 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA5 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA5 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB5EN : Counter/Timer B5 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B5 Disable.

1 : EN

Counter/Timer B5 Enable.

End of enumeration elements list.

TMRB5CLK : Counter/Timer B5 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA5

Clock source is CTIMERA5 OUT.

21 : CTMRA0

Clock source is CTIMERA0 OUT.

22 : CTMRB0

Clock source is CTIMERB0 OUT.

23 : CTMRA6

Clock source is CTIMERA6 OUT.

24 : CTMRB6

Clock source is CTIMERB6 OUT.

25 : CTMRB1

Clock source is CTIMERB1 OUT.

26 : CTMRB2

Clock source is CTIMERB2 OUT.

27 : CTMRB3

Clock source is CTIMERB3 OUT.

28 : CTMRB4

Clock source is CTIMERB4 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB5FN : Counter/Timer B5 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B5, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B5, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B5, assert, count to CMPR1B5, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B5, assert, count to CMPR1B5, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB5IE0 : Counter/Timer B5 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B5 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B5 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB5IE1 : Counter/Timer B5 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B5 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B5 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB5CLR : Counter/Timer B5 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B5 to run

1 : CLEAR

Holds counter/timer B5 at 0x0000.

End of enumeration elements list.

TMRB5POL : Counter/Timer B5 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB5 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB5 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK5 : Counter/Timer A5/B5 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A5/B5 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A5/B5 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA5

Counter/Timer A5 Compare Registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA5 CMPRAUXA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A5 CMPR3A5

CMPR2A5 : Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A5 : Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB5

Counter/Timer B5 Compare Registers
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB5 CMPRAUXB5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B5 CMPR3B5

CMPR2B5 : Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B5 : Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX5

Counter/Timer Auxiliary
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX5 AUX5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA5LMT TMRA5TRIG TMRA5NOSYNC TMRA5TINV TMRA5POL23 TMRA5EN23 TMRB5LMT TMRB5TRIG TMRB5NOSYNC TMRB5TINV TMRB5POL23 TMRB5EN23

TMRA5LMT : Counter/Timer A5 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA5TRIG : Counter/Timer A5 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : STIMER

Trigger source is STimer Interrupt. Only Active When CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER interrupt

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A4OUT

Trigger source is CTIMERA4 OUT.

5 : B4OUT

Trigger source is CTIMERB4 OUT.

6 : A2OUT

Trigger source is CTIMERA2 OUT.

7 : B2OUT

Trigger source is CTIMERB2 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A0OUT2

Trigger source is CTIMERA0 OUT2.

11 : B0OUT2

Trigger source is CTIMERB0 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRA5NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA5TINV : Counter/Timer A5 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA5POL23 : Counter/Timer A5 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORMAL

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA5EN23 : Counter/Timer A5 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB5LMT : Counter/Timer B5 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB5TRIG : Counter/Timer B5 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A5OUT

Trigger source is CTIMERA5 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A6OUT

Trigger source is CTIMERA6 OUT.

5 : B6OUT

Trigger source is CTIMERB6 OUT.

6 : A1OUT

Trigger source is CTIMERA1 OUT.

7 : B1OUT

Trigger source is CTIMERB1 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A0OUT2

Trigger source is CTIMERA0 OUT2.

11 : B0OUT2

Trigger source is CTIMERB0 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRB5NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB5TINV : Counter/Timer B5 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB5POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB5EN23 : Counter/Timer B5 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


CTRL0

Counter/Timer Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA0EN TMRA0CLK TMRA0FN TMRA0IE0 TMRA0IE1 TMRA0CLR TMRA0POL TMRB0EN TMRB0CLK TMRB0FN TMRB0IE0 TMRB0IE1 TMRB0CLR TMRB0POL CTLINK0

TMRA0EN : Counter/Timer A0 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A0 Disable.

1 : EN

Counter/Timer A0 Enable.

End of enumeration elements list.

TMRA0CLK : Counter/Timer A0 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB0

Clock source is CTIMERB0 OUT.

21 : CTMRA1

Clock source is CTIMERA1 OUT.

22 : CTMRB1

Clock source is CTIMERB1 OUT.

23 : CTMRA2

Clock source is CTIMERA2 OUT.

24 : CTMRB2

Clock source is CTIMERB2 OUT.

25 : CTMRB3

Clock source is CTIMERB3 OUT.

26 : CTMRB4

Clock source is CTIMERB4 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA0FN : Counter/Timer A0 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A0, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA0IE0 : Counter/Timer A0 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A0 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A0 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA0IE1 : Counter/Timer A0 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A0 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A0 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA0CLR : Counter/Timer A0 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A0 to run

1 : CLEAR

Holds counter/timer A0 at 0x0000.

End of enumeration elements list.

TMRA0POL : Counter/Timer A0 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA0 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA0 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB0EN : Counter/Timer B0 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B0 Disable.

1 : EN

Counter/Timer B0 Enable.

End of enumeration elements list.

TMRB0CLK : Counter/Timer B0 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA0

Clock source is CTIMERA0 OUT.

21 : CTMRB1

Clock source is CTIMERB1 OUT.

22 : CTMRA1

Clock source is CTIMERA1 OUT.

23 : CTMRA2

Clock source is CTIMERA2 OUT.

24 : CTMRB2

Clock source is CTIMERB2 OUT.

25 : CTMRB3

Clock source is CTIMERB3 OUT.

26 : CTMRB4

Clock source is CTIMERB4 OUT.

27 : CTMRB5

Clock source is CTIMERB5 OUT.

28 : CTMRB6

Clock source is CTIMERB6 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB0FN : Counter/Timer B0 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B0, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB0IE0 : Counter/Timer B0 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B0 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B0 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB0IE1 : Counter/Timer B0 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B0 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B0 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB0CLR : Counter/Timer B0 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B0 to run

1 : CLEAR

Holds counter/timer B0 at 0x0000.

End of enumeration elements list.

TMRB0POL : Counter/Timer B0 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB0 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB0 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK0 : Counter/Timer A0/B0 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A0/B0 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A0/B0 timers into a single 32-bit timer.

End of enumeration elements list.


TMR6

Counter/Timer Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR6 TMR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA6 CTTMRB6

CTTMRA6 : Counter/Timer A6.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB6 : Counter/Timer B6.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA6

Counter/Timer A6 Compare Registers
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA6 CMPRA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A6 CMPR1A6

CMPR0A6 : Counter/Timer A6 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A6 : Counter/Timer A6 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB6

Counter/Timer B6 Compare Registers
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB6 CMPRB6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B6 CMPR1B6

CMPR0B6 : Counter/Timer B6 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B6 : Counter/Timer B6 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL6

Counter/Timer Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL6 CTRL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA6EN TMRA6CLK TMRA6FN TMRA6IE0 TMRA6IE1 TMRA6CLR TMRA6POL TMRB6EN TMRB6CLK TMRB6FN TMRB6IE0 TMRB6IE1 TMRB6CLR TMRB6POL CTLINK6

TMRA6EN : Counter/Timer A6 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A6 Disable.

1 : EN

Counter/Timer A6 Enable.

End of enumeration elements list.

TMRA6CLK : Counter/Timer A6 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB6

Clock source is CTIMERB6 OUT.

21 : CTMRA3

Clock source is CTIMERA3 OUT.

22 : CTMRB3

Clock source is CTIMERB3 OUT.

23 : CTMRA7

Clock source is CTIMERA7 OUT.

24 : CTMRB7

Clock source is CTIMERB7 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB2

Clock source is CTIMERB2 OUT.

28 : CTMRB4

Clock source is CTIMERB4 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA6FN : Counter/Timer A6 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A6, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A6, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A6, assert, count to CMPR1A6, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A6, assert, count to CMPR1A6, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA6IE0 : Counter/Timer A6 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A6 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A6 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA6IE1 : Counter/Timer A6 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A6 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A6 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA6CLR : Counter/Timer A6 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A6 to run

1 : CLEAR

Holds counter/timer A6 at 0x0000.

End of enumeration elements list.

TMRA6POL : Counter/Timer A6 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA6 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA6 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB6EN : Counter/Timer B6 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B6 Disable.

1 : EN

Counter/Timer B6 Enable.

End of enumeration elements list.

TMRB6CLK : Counter/Timer B6 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA6

Clock source is CTIMERA6 OUT.

21 : CTMRA3

Clock source is CTIMERA3 OUT.

22 : CTMRB3

Clock source is CTIMERB3 OUT.

23 : CTMRA7

Clock source is CTIMERA7 OUT.

24 : CTMRB7

Clock source is CTIMERB7 OUT.

25 : CTMRB0

Clock source is CTIMERB0 OUT.

26 : CTMRB1

Clock source is CTIMERB1 OUT.

27 : CTMRB2

Clock source is CTIMERB2 OUT.

28 : CTMRB4

Clock source is CTIMERB4 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB6FN : Counter/Timer B6 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B6, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B6, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B6, assert, count to CMPR1B6, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B6, assert, count to CMPR1B6, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB6IE0 : Counter/Timer B6 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B6 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B6 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB6IE1 : Counter/Timer B6 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B6 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B6 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB6CLR : Counter/Timer B6 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B6 to run

1 : CLEAR

Holds counter/timer B6 at 0x0000.

End of enumeration elements list.

TMRB6POL : Counter/Timer B6 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB6 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB6 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK6 : Counter/Timer A6/B6 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A6/B6 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A6/B6 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA6

Counter/Timer A6 Compare Registers
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA6 CMPRAUXA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A6 CMPR3A6

CMPR2A6 : Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A6 : Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB6

Counter/Timer B6 Compare Registers
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB6 CMPRAUXB6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B6 CMPR3B6

CMPR2B6 : Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B6 : Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX6

Counter/Timer Auxiliary
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX6 AUX6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA6LMT TMRA6TRIG TMRA6NOSYNC TMRA6TINV TMRA6POL23 TMRA6EN23 TMRB6LMT TMRB6TRIG TMRB6NOSYNC TMRB6TINV TMRB6POL23 TMRB6EN23

TMRA6LMT : Counter/Timer A6 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA6TRIG : Counter/Timer A6 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B6OUT

Trigger source is CTIMERB6 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A5OUT

Trigger source is CTIMERA5 OUT.

5 : B5OUT

Trigger source is CTIMERB5 OUT.

6 : A1OUT

Trigger source is CTIMERA1 OUT.

7 : B1OUT

Trigger source is CTIMERB1 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A2OUT2

Trigger source is CTIMERA2 OUT2.

11 : B2OUT2

Trigger source is CTIMERBb OUT2.

12 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B0OUT2DUAL

Trigger source is CTIMERB0 OUT2, dual edge.

15 : A0OUT2DUAL

Trigger source is CTIMERA0 OUT2, dual edge.

End of enumeration elements list.

TMRA6NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA6TINV : Counter/Timer A6 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA6POL23 : Counter/Timer A6 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA6EN23 : Counter/Timer A6 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB6LMT : Counter/Timer B6 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB6TRIG : Counter/Timer B6 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A6OUT

Trigger source is CTIMERA6 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A4OUT

Trigger source is CTIMERA4 OUT.

5 : B4OUT

Trigger source is CTIMERB4 OUT.

6 : A1OUT

Trigger source is CTIMERA1 OUT.

7 : B1OUT

Trigger source is CTIMERB1 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A2OUT2

Trigger source is CTIMERA2 OUT2.

11 : B2OUT2

Trigger source is CTIMERB2 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B0OUT2DUAL

Trigger source is CTIMERB0 OUT2, dual edge.

15 : A0OUT2DUAL

Trigger source is CTIMERA0 OUT2, dual edge.

End of enumeration elements list.

TMRB6NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB6TINV : Counter/Timer B6 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB6POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB6EN23 : Counter/Timer B6 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.


TMR7

Counter/Timer Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR7 TMR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTTMRA7 CTTMRB7

CTTMRA7 : Counter/Timer A7.
bits : 0 - 15 (16 bit)
access : read-write

CTTMRB7 : Counter/Timer B7.
bits : 16 - 47 (32 bit)
access : read-write


CMPRA7

Counter/Timer A7 Compare Registers
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRA7 CMPRA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0A7 CMPR1A7

CMPR0A7 : Counter/Timer A7 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1A7 : Counter/Timer A7 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CMPRB7

Counter/Timer B7 Compare Registers
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRB7 CMPRB7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR0B7 CMPR1B7

CMPR0B7 : Counter/Timer B3 Compare Register 0.
bits : 0 - 15 (16 bit)
access : read-write

CMPR1B7 : Counter/Timer B3 Compare Register 1.
bits : 16 - 47 (32 bit)
access : read-write


CTRL7

Counter/Timer Control
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL7 CTRL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA7EN TMRA7CLK TMRA7FN TMRA7IE0 TMRA7IE1 TMRA7CLR TMRA7POL TMRB7EN TMRB7CLK TMRB7FN TMRB7IE0 TMRB7IE1 TMRB7CLR TMRB7POL CTLINK7

TMRA7EN : Counter/Timer A7 Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer A7 Disable.

1 : EN

Counter/Timer A7 Enable.

End of enumeration elements list.

TMRA7CLK : Counter/Timer A7 Clock Select.
bits : 1 - 6 (6 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINA.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRB7

Clock source is CTIMERB7 OUT.

21 : CTMRA2

Clock source is CTIMERA2 OUT.

22 : CTMRB2

Clock source is CTIMERB2 OUT.

23 : CTMRA0

Clock source is CTIMERA0 OUT.

24 : CTMRB0

Clock source is CTIMERB0 OUT.

25 : CTMRB1

Clock source is CTIMERB1 OUT.

26 : CTMRB3

Clock source is CTIMERB3 OUT.

27 : CTMRB4

Clock source is CTIMERB4 OUT.

28 : CTMRB5

Clock source is CTIMERB5 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRA7FN : Counter/Timer A7 Function Select.
bits : 6 - 14 (9 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0A7, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A7, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0A7, assert, count to CMPR1A7, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0A7, assert, count to CMPR1A7, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRA7IE0 : Counter/Timer A7 Interrupt Enable bit based on COMPR0.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A7 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer A7 to generate an interrupt based on COMPR0.

End of enumeration elements list.

TMRA7IE1 : Counter/Timer A7 Interrupt Enable bit based on COMPR1.
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer A7 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer A7 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRA7CLR : Counter/Timer A7 Clear bit.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer A7 to run

1 : CLEAR

Holds counter/timer A7 at 0x0000.

End of enumeration elements list.

TMRA7POL : Counter/Timer A7 output polarity.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINA7 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINA7 pin is the inverse of the timer output.

End of enumeration elements list.

TMRB7EN : Counter/Timer B7 Enable bit.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : DIS

Counter/Timer B7 Disable.

1 : EN

Counter/Timer B7 Enable.

End of enumeration elements list.

TMRB7CLK : Counter/Timer B7 Clock Select.
bits : 17 - 38 (22 bit)
access : read-write

Enumeration:

0 : TMRPIN

Clock source is TMRPINB.

1 : HFRC_DIV4

Clock source is the HFRC / 4

2 : HFRC_DIV16

Clock source is HFRC / 16

3 : HFRC_DIV256

Clock source is HFRC / 256

4 : HFRC_DIV1024

Clock source is HFRC / 1024

5 : HFRC_DIV4K

Clock source is HFRC / 4096

6 : XT

Clock source is the XT (uncalibrated).

7 : XT_DIV2

Clock source is XT / 2

8 : XT_DIV16

Clock source is XT / 16

9 : XT_DIV128

Clock source is XT / 128

10 : LFRC_DIV2

Clock source is LFRC / 2

11 : LFRC_DIV32

Clock source is LFRC / 32

12 : LFRC_DIV1K

Clock source is LFRC / 1024

13 : LFRC

Clock source is LFRC

14 : RTC_100HZ

Clock source is 100 Hz from the current RTC oscillator.

15 : HCLK_DIV4

Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode)

16 : XT_DIV4

Clock source is XT / 4

17 : XT_DIV8

Clock source is XT / 8

18 : XT_DIV32

Clock source is XT / 32

20 : CTMRA7

Clock source is CTIMERA7 OUT.

21 : CTMRA2

Clock source is CTIMERA2 OUT.

22 : CTMRB2

Clock source is CTIMERB2 OUT.

23 : CTMRA0

Clock source is CTIMERA0 OUT.

24 : CTMRB0

Clock source is CTIMERB0 OUT.

25 : CTMRB1

Clock source is CTIMERB1 OUT.

26 : CTMRB3

Clock source is CTIMERB3 OUT.

27 : CTMRB4

Clock source is CTIMERB4 OUT.

28 : CTMRB5

Clock source is CTIMERB5 OUT.

29 : BUCKBLE

Clock source is BLE buck converter TON pulses.

30 : BUCKB

Clock source is Memory buck converter TON pulses.

31 : BUCKA

Clock source is CPU buck converter TON pulses.

End of enumeration elements list.

TMRB7FN : Counter/Timer B7 Function Select.
bits : 22 - 46 (25 bit)
access : read-write

Enumeration:

0 : SINGLECOUNT

Single count (output toggles and sticks). Count to CMPR0B7, stop.

1 : REPEATEDCOUNT

Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B7, restart.

2 : PULSE_ONCE

Pulse once (aka one-shot). Count to CMPR0B7, assert, count to CMPR1B7, deassert, stop.

3 : PULSE_CONT

Pulse continously. Count to CMPR0B7, assert, count to CMPR1B7, deassert, restart.

4 : SINGLEPATTERN

Single pattern.

5 : REPEATPATTERN

Repeated pattern.

6 : CONTINUOUS

Continuous run (aka Free Run). Count continuously.

7 : ALTPWN

Alternate PWM

End of enumeration elements list.

TMRB7IE0 : Counter/Timer B7 Interrupt Enable bit for COMPR0.
bits : 25 - 50 (26 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B7 from generating an interrupt based on COMPR0.

1 : EN

Enable counter/timer B7 to generate an interrupt based on COMPR0

End of enumeration elements list.

TMRB7IE1 : Counter/Timer B7 Interrupt Enable bit for COMPR1.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable counter/timer B7 from generating an interrupt based on COMPR1.

1 : EN

Enable counter/timer B7 to generate an interrupt based on COMPR1.

End of enumeration elements list.

TMRB7CLR : Counter/Timer B7 Clear bit.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : RUN

Allow counter/timer B7 to run

1 : CLEAR

Holds counter/timer B7 at 0x0000.

End of enumeration elements list.

TMRB7POL : Counter/Timer B7 output polarity.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : NORMAL

The polarity of the TMRPINB7 pin is the same as the timer output.

1 : INVERTED

The polarity of the TMRPINB7 pin is the inverse of the timer output.

End of enumeration elements list.

CTLINK7 : Counter/Timer A7/B7 Link bit.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : TWO_16BIT_TIMERS

Use A7/B7 timers as two independent 16-bit timers (default).

1 : 32BIT_TIMER

Link A7/B7 timers into a single 32-bit timer.

End of enumeration elements list.


CMPRAUXA7

Counter/Timer A7 Compare Registers
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXA7 CMPRAUXA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2A7 CMPR3A7

CMPR2A7 : Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3A7 : Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A.
bits : 16 - 47 (32 bit)
access : read-write


CMPRAUXB7

Counter/Timer B7 Compare Registers
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPRAUXB7 CMPRAUXB7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPR2B7 CMPR3B7

CMPR2B7 : Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B.
bits : 0 - 15 (16 bit)
access : read-write

CMPR3B7 : Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B.
bits : 16 - 47 (32 bit)
access : read-write


AUX7

Counter/Timer Auxiliary
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUX7 AUX7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRA7LMT TMRA7TRIG TMRA7NOSYNC TMRA7TINV TMRA7POL23 TMRA7EN23 TMRB7LMT TMRB7TRIG TMRB7NOSYNC TMRB7TINV TMRB7POL23 TMRB7EN23

TMRA7LMT : Counter/Timer A7 Pattern Limit Count.
bits : 0 - 6 (7 bit)
access : read-write

TMRA7TRIG : Counter/Timer A7 Trigger Select.
bits : 7 - 17 (11 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : B7OUT

Trigger source is CTIMERB7 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A1OUT

Trigger source is CTIMERA1 OUT.

5 : B1OUT

Trigger source is CTIMERB1 OUT.

6 : A4OUT

Trigger source is CTIMERA4 OUT.

7 : B4OUT

Trigger source is CTIMERB4 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A2OUT2

Trigger source is CTIMERA2 OUT2.

11 : B2OUT2

Trigger source is CTIMERB2 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A5OUT2DUAL

Trigger source is CTIMERA5 OUT2, dual edge.

14 : B4OUT2DUAL

Trigger source is CTIMERB4 OUT2, dual edge.

15 : A4OUT2DUAL

Trigger source is CTIMERA4 OUT2, dual edge.

End of enumeration elements list.

TMRA7NOSYNC : Source clock synchronization control.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRA7TINV : Counter/Timer A7 Invert on trigger.
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRA7POL23 : Counter/Timer A7 Upper output polarity
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRA7EN23 : Counter/Timer A7 Upper compare enable.
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.

TMRB7LMT : Counter/Timer B7 Pattern Limit Count.
bits : 16 - 37 (22 bit)
access : read-write

TMRB7TRIG : Counter/Timer B7 Trigger Select.
bits : 23 - 49 (27 bit)
access : read-write

Enumeration:

0 : DIS

Trigger source is disabled.

1 : A7OUT

Trigger source is CTIMERA7 OUT.

2 : B3OUT

Trigger source is CTIMERB3 OUT.

3 : A3OUT

Trigger source is CTIMERA3 OUT.

4 : A5OUT

Trigger source is CTIMERA5 OUT.

5 : B5OUT

Trigger source is CTIMERB5 OUT.

6 : A2OUT

Trigger source is CTIMERA2 OUT.

7 : B2OUT

Trigger source is CTIMERB2 OUT.

8 : B3OUT2

Trigger source is CTIMERB3 OUT2.

9 : A3OUT2

Trigger source is CTIMERA3 OUT2.

10 : A2OUT2

Trigger source is CTIMERA2 OUT2.

11 : B2OUT2

Trigger source is CTIMERB2 OUT2.

12 : A6OUT2DUAL

Trigger source is CTIMERA6 OUT2, dual edge.

13 : A7OUT2DUAL

Trigger source is CTIMERA7 OUT2, dual edge.

14 : B1OUT2DUAL

Trigger source is CTIMERB1 OUT2, dual edge.

15 : A1OUT2DUAL

Trigger source is CTIMERA1 OUT2, dual edge.

End of enumeration elements list.

TMRB7NOSYNC : Source clock synchronization control.
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : DIS

Synchronization on source clock

1 : NOSYNC

No synchronization on source clock

End of enumeration elements list.

TMRB7TINV : Counter/Timer B7 Invert on trigger.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable invert on trigger

1 : EN

Enable invert on trigger

End of enumeration elements list.

TMRB7POL23 : Upper output polarity
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : NORM

Upper output normal polarity

1 : INV

Upper output inverted polarity.

End of enumeration elements list.

TMRB7EN23 : Counter/Timer B7 Upper compare enable.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : DIS

Disable enhanced functions.

0 : EN

Enable enhanced functions.

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.