FIFO

FIFOPTR

FIFOTHR

FIFOPOP

FIFOPUSH

FIFOCTRL

FIFOLOC

INTEN

INTSTAT

INTCLR

INTSET

CLKCFG

SUBMODCTRL

CMD

DCX

OFFSETHI

CMDSTAT

DMATRIGEN

DMATRIGSTAT

DMACFG

DMATOTCOUNT

DMATARGADDR

DMASTAT

CQCFG

CQADDR

CQSTAT

CQFLAGS

CQSETCLEAR

CQPAUSEEN

CQCURIDX

CQENDIDX

STATUS

MSPICFG

MI2CCFG

DEVCFG

IOMDBG

FIFO : FIFO direct access. Only locations 0 - 3F will return valid information.
bits : 0 - 31 (32 bit)
access : read-write

FIFO0SIZ : The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)
bits : 0 - 7 (8 bit)
access : read-write

FIFO0REM : The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)
bits : 8 - 23 (16 bit)
access : read-write

FIFO1SIZ : The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)
bits : 16 - 39 (24 bit)
access : read-write

FIFO1REM : The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)
bits : 24 - 55 (32 bit)
access : read-write

FIFORTHR : FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations.
bits : 0 - 5 (6 bit)
access : read-write

FIFOWTHR : FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations.
bits : 8 - 21 (14 bit)
access : read-write

FIFODOUT : This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.
bits : 0 - 31 (32 bit)
access : read-write

FIFODIN : This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).
bits : 0 - 31 (32 bit)
access : read-write

POPWR : Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode.
bits : 0 - 0 (1 bit)
access : read-write

FIFORSTN : Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset.
bits : 1 - 2 (2 bit)
access : read-write

FIFOWPTR : Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.
bits : 0 - 3 (4 bit)
access : read-write

FIFORPTR : Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.
bits : 8 - 19 (12 bit)
access : read-write

CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write

THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo.
bits : 2 - 4 (3 bit)
access : read-write

FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write

NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write

IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write

ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write

START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write

STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write

ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write

DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write

DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write

CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write

CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write

CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write

CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write

THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo.
bits : 2 - 4 (3 bit)
access : read-write

FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write

NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write

IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write

ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write

START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write

STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write

ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write

DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write

DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write

CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write

CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write

CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write

CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write

THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo.
bits : 2 - 4 (3 bit)
access : read-write

FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write

NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write

IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write

ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write

START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write

STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write

ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write

DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write

DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write

CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write

CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write

CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write

CMDCMP : Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.
bits : 0 - 0 (1 bit)
access : read-write

THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write

FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo.
bits : 2 - 4 (3 bit)
access : read-write

FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write

NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write

IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write

ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write

START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write

STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write

ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write

DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write

DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write

CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write

CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write

CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write

IOCLKEN : Enable for the interface clock. Must be enabled prior to executing any IO operations.
bits : 0 - 0 (1 bit)
access : read-write

FSEL : Select the input clock frequency.
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV3 : Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled will provide the divided by 3 clock as the source to the programmable divider.
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVEN : Enable clock division by TOTPER and LOWPER
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOWPER : Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1. Only applicable when DIVEN = 1.
bits : 16 - 39 (24 bit)
access : read-write

TOTPER : Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The source clock is selected by FSEL. Only applicable when DIVEN = 1.
bits : 24 - 55 (32 bit)
access : read-write

SMOD0EN : Submodule 0 enable (1) or disable (0)
bits : 0 - 0 (1 bit)
access : read-write

SMOD0TYPE : Submodule 0 module type. This is the SPI Master interface.
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMOD1EN : Submodule 1 enable (1) or disable (0)
bits : 4 - 8 (5 bit)
access : read-write

SMOD1TYPE : Submodule 0 module type. This is the I2C Master interface
bits : 5 - 12 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMD : Command for submodule.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFSETCNT : Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If offsetcnt == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.
bits : 5 - 11 (7 bit)
access : read-write

CONT : Contine to hold the bus after the current transaction if set to a 1 with a new command issued.
bits : 7 - 14 (8 bit)
access : read-write

TSIZE : Defines the transaction size in bytes. The offset transfer is not included in this size.
bits : 8 - 27 (20 bit)
access : read-write

CMDSEL : Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions
bits : 20 - 41 (22 bit)
access : read-write

OFFSETLO : This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command.
bits : 24 - 55 (32 bit)
access : read-write

CE0OUT : Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output.
bits : 0 - 0 (1 bit)
access : read-write

CE1OUT : Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output.
bits : 1 - 2 (2 bit)
access : read-write

CE2OUT : Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output.
bits : 2 - 4 (3 bit)
access : read-write

CE3OUT : Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output.
bits : 3 - 6 (4 bit)
access : read-write

DCXEN : Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte, and high during transmission of data bytes.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFSETHI : Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register
bits : 0 - 15 (16 bit)
access : read-write

CCMD : current command that is being executed
bits : 0 - 4 (5 bit)
access : read-write

CMDSTAT : The current status of the command execution.
bits : 5 - 12 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSIZE : The current number of bytes still to be transferred with this command. This field will count down to zero.
bits : 8 - 27 (20 bit)
access : read-write

DCMDCMPEN : Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or
bits : 0 - 0 (1 bit)
access : read-write

DTHREN : Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, the CMDCMP trigger must also be enabled to transfer the remaining read FIFO data to SRAM.
bits : 1 - 2 (2 bit)
access : read-write

DCMDCMP : Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.
bits : 0 - 0 (1 bit)
access : read-write

DTHR : Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 1 - 2 (2 bit)
access : read-write

DTOTCMP : DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.
bits : 2 - 4 (3 bit)
access : read-write

DMAEN : DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADIR : Direction
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAPRI : Sets the Priority of the DMA request
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWROFF : Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOTCOUNT : Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 0 - 11 (12 bit)
access : read-write

TARGADDR : Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
bits : 0 - 19 (20 bit)
access : read-write

TARGADDR28 : Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash
bits : 28 - 56 (29 bit)
access : read-write

DMATIP : DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

DMACPL : DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0, and will also be cleared when a new DMA is started.
bits : 1 - 2 (2 bit)
access : read-write

DMAERR : DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set, this bit will remain set until cleared by software.
bits : 2 - 4 (3 bit)
access : read-write

CQEN : Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQPRI : Sets the Priority of the command queue dma request
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQADDR : Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary
bits : 2 - 21 (20 bit)
access : read-write

CQADDR28 : Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access
bits : 28 - 56 (29 bit)
access : read-write

CQTIP : Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.
bits : 0 - 0 (1 bit)
access : read-write

CQPAUSED : Command queue operation is currently paused.
bits : 1 - 2 (2 bit)
access : read-write

CQERR : Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.
bits : 2 - 4 (3 bit)
access : read-write

CQFLAGS : Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.
bits : 0 - 15 (16 bit)
access : read-write

CQIRQMASK : Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE
bits : 16 - 47 (32 bit)
access : read-write

CQFSET : Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 0 - 7 (8 bit)
access : read-write

CQFTGL : Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 8 - 23 (16 bit)
access : read-write

CQFCLR : Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field
bits : 16 - 39 (24 bit)
access : read-write

CQPEN : Enables the specified event to pause command processing when active
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQCURIDX : Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write

CQENDIDX : Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write

ERR : Bit has been deprecated. Please refer to the other error indicators. This will always return 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMDACT : Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDLEST : indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPOL : selects SPI polarity.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPHA : selects SPI phase.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULLDUP : Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo
bits : 2 - 4 (3 bit)
access : read-write

WTFC : enables write mode flow control.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDFC : enables read mode flow control.
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MOSIINV : inverts MOSI when flow control is enabled.
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTFCIRQ : selects the write mode flow control signal.
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTFCPOL : selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers).
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDFCPOL : selects the read flow control signal polarity.
bits : 22 - 44 (23 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPILSB : Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.
bits : 23 - 46 (24 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINDLY : Delay tap to use for the input signal (MISO). This gives more hold time on the input data.
bits : 24 - 50 (27 bit)
access : read-write

DOUTDLY : Delay tap to use for the output signal (MOSI). This give more hold time on the output data
bits : 27 - 56 (30 bit)
access : read-write

MSPIRST : Not used. To reset the module, toggle the SMOD_EN for the module
bits : 30 - 60 (31 bit)
access : read-write

ADDRSZ : Sets the I2C master device address size to either 7b (0) or 10b (1).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CLSB : Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ARBEN : Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDADLY : Delay to enable on the SDA output. Values are 0x0-0x3.
bits : 4 - 9 (6 bit)
access : read-write

MI2CRST : Not used. To reset the module, toggle the SMOD_EN for the module
bits : 6 - 12 (7 bit)
access : read-write

SCLENDLY : Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping.
bits : 8 - 19 (12 bit)
access : read-write

SDAENDLY : Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock
bits : 12 - 27 (16 bit)
access : read-write

SMPCNT : Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured
bits : 16 - 39 (24 bit)
access : read-write

STRDIS : Disable detection of clock stretch events smaller than 1 cycle
bits : 24 - 48 (25 bit)
access : read-write

DEVADDR : I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address.
bits : 0 - 9 (10 bit)
access : read-write

DBGEN : Debug Enable. Setting bit will enable the update of data within this register, otherwise it is clock gated for power savings
bits : 0 - 0 (1 bit)
access : read-write

IOCLKON : IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 1 - 2 (2 bit)
access : read-write

APBCLKON : APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 2 - 4 (3 bit)
access : read-write

DBGDATA : Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers.
bits : 3 - 34 (32 bit)
access : read-write