CTRL

TXFIFO

MSPICFG

PADCFG

PADOUTEN

FLASH

SCRAMBLING

RXFIFO

TXENTRIES

RXENTRIES

THRESHOLD

INTEN

INTSTAT

INTCLR

INTSET

DMACFG

DMASTAT

DMATARGADDR

DMADEVADDR

DMATOTCOUNT

DMABCOUNT

DMATHRESH

CQCFG

CQADDR

CQSTAT

CQFLAGS

CQSETCLEAR

CQPAUSE

CQCURIDX

CQENDIDX

CFG

ADDR

INSTR

START : Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set).
bits : 0 - 0 (1 bit)
access : read-write

STATUS : Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer.
bits : 1 - 2 (2 bit)
access : read-write

BUSY : Command status: 1 indicates controller is busy (command in progress)
bits : 2 - 4 (3 bit)
access : read-write

QUADCMD : Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers).
bits : 3 - 6 (4 bit)
access : read-write

BIGENDIAN : 1 indicates data in FIFO is in big endian format (MSB first) 0 indicates little endian data (default, LSB first).
bits : 6 - 12 (7 bit)
access : read-write

ENTURN : Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register).
bits : 7 - 14 (8 bit)
access : read-write

SENDA : Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)
bits : 8 - 16 (9 bit)
access : read-write

SENDI : Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)
bits : 9 - 18 (10 bit)
access : read-write

TXRX : 1 Indicates a TX operation, 0 indicates an RX operation of XFERBYTES
bits : 10 - 20 (11 bit)
access : read-write

PIOSCRAMBLE : Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device.
bits : 11 - 22 (12 bit)
access : read-write

XFERBYTES : Number of bytes to transmit or receive (based on TXRX bit)
bits : 16 - 47 (32 bit)
access : read-write

TXFIFO : Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set.
bits : 0 - 31 (32 bit)
access : read-write

APBCLK : Enable continuous APB clock. For power-efficient operation, APBCLK should be set to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXCAP : Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However, to accommodate chip/pad/board delays, a setting of RXCAP of 1 is expected to be used to align the capture point with the return data window. This bit is used in conjunction with RXNEG to provide 4 unique capture points, all about 10 ns apart.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXNEG : Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation, it is expected that RXNEG will be set to 0.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXNEG : Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL).
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IOMSEL : Selects which IOM is selected for CQ handshake status.
bits : 4 - 10 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV : Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data).
bits : 8 - 21 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFORESET : Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May be used to manually flush the FIFO in error handling.
bits : 29 - 58 (30 bit)
access : read-write

IPRSTN : IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus.
bits : 30 - 60 (31 bit)
access : read-write

PRSTN : Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and transfer state machines). 1=normal operation, 0=in reset.
bits : 31 - 62 (32 bit)
access : read-write

OUT3 : Output pad 3 configuration. 0=data[3] 1=CLK
bits : 0 - 0 (1 bit)
access : read-write

OUT4 : Output pad 4 configuration. 0=data[4] 1=data[0]
bits : 1 - 2 (2 bit)
access : read-write

OUT5 : Output pad 5 configuration. 0=data[5] 1=data[1]
bits : 2 - 4 (3 bit)
access : read-write

OUT6 : Output pad 6 configuration. 0=data[6] 1=data[2]
bits : 3 - 6 (4 bit)
access : read-write

OUT7 : Output pad 7 configuration. 0=data[7] 1=data[3]
bits : 4 - 8 (5 bit)
access : read-write

IN0 : Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]
bits : 16 - 33 (18 bit)
access : read-write

IN1 : Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]
bits : 18 - 36 (19 bit)
access : read-write

IN2 : Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]
bits : 19 - 38 (20 bit)
access : read-write

IN3 : Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]
bits : 20 - 40 (21 bit)
access : read-write

REVCS : Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines
bits : 21 - 42 (22 bit)
access : read-write

OUTEN : Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock.
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XIPEN : Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF.
bits : 0 - 0 (1 bit)
access : read-write

XIPACK : Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XIPBIGENDIAN : Indicates whether XIP/AUTO DMA data transfers are in big or little endian format
bits : 4 - 8 (5 bit)
access : read-write

XIPENTURN : Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles
bits : 5 - 10 (6 bit)
access : read-write

XIPSENDA : Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)
bits : 6 - 12 (7 bit)
access : read-write

XIPSENDI : Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)
bits : 7 - 14 (8 bit)
access : read-write

XIPMIXED : Reserved. Set to 0x0
bits : 8 - 18 (11 bit)
access : read-write

WRITEINSTR : Write command sent for DMA operations
bits : 16 - 39 (24 bit)
access : read-write

READINSTR : Read command sent to flash for DMA/XIP operations
bits : 24 - 55 (32 bit)
access : read-write

SCRSTART : Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range.
bits : 0 - 9 (10 bit)
access : read-write

SCREND : Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range.
bits : 16 - 41 (26 bit)
access : read-write

SCRENABLE : Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0, data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range.
bits : 31 - 62 (32 bit)
access : read-write

RXFIFO : Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set.
bits : 0 - 31 (32 bit)
access : read-write

TXENTRIES : Number of 32-bit words/entries in TX FIFO
bits : 0 - 4 (5 bit)
access : read-write

RXENTRIES : Number of 32-bit words/entries in RX FIFO
bits : 0 - 4 (5 bit)
access : read-write

TXTHRESH : Number of entries in TX FIFO that cause TXF interrupt
bits : 0 - 4 (5 bit)
access : read-write

RXTHRESH : Number of entries in TX FIFO that cause RXE interrupt
bits : 8 - 20 (13 bit)
access : read-write

CMDCMP : Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.
bits : 0 - 0 (1 bit)
access : read-write

TXE : Transmit FIFO empty.
bits : 1 - 2 (2 bit)
access : read-write

TXO : Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
bits : 2 - 4 (3 bit)
access : read-write

RXU : Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
bits : 3 - 6 (4 bit)
access : read-write

RXO : Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)
bits : 4 - 8 (5 bit)
access : read-write

RXF : Receive FIFO full
bits : 5 - 10 (6 bit)
access : read-write

DCMP : DMA Complete Interrupt
bits : 6 - 12 (7 bit)
access : read-write

DERR : DMA Error Interrupt
bits : 7 - 14 (8 bit)
access : read-write

CQCMP : Command Queue Complete Interrupt
bits : 8 - 16 (9 bit)
access : read-write

CQUPD : Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.
bits : 9 - 18 (10 bit)
access : read-write

CQPAUSED : Command Queue is Paused.
bits : 10 - 20 (11 bit)
access : read-write

CQERR : Command Queue Error Interrupt
bits : 11 - 22 (12 bit)
access : read-write

SCRERR : Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.
bits : 12 - 24 (13 bit)
access : read-write

CMDCMP : Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.
bits : 0 - 0 (1 bit)
access : read-write

TXE : Transmit FIFO empty.
bits : 1 - 2 (2 bit)
access : read-write

TXO : Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
bits : 2 - 4 (3 bit)
access : read-write

RXU : Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
bits : 3 - 6 (4 bit)
access : read-write

RXO : Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)
bits : 4 - 8 (5 bit)
access : read-write

RXF : Receive FIFO full
bits : 5 - 10 (6 bit)
access : read-write

DCMP : DMA Complete Interrupt
bits : 6 - 12 (7 bit)
access : read-write

DERR : DMA Error Interrupt
bits : 7 - 14 (8 bit)
access : read-write

CQCMP : Command Queue Complete Interrupt
bits : 8 - 16 (9 bit)
access : read-write

CQUPD : Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.
bits : 9 - 18 (10 bit)
access : read-write

CQPAUSED : Command Queue is Paused.
bits : 10 - 20 (11 bit)
access : read-write

CQERR : Command Queue Error Interrupt
bits : 11 - 22 (12 bit)
access : read-write

SCRERR : Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.
bits : 12 - 24 (13 bit)
access : read-write

CMDCMP : Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.
bits : 0 - 0 (1 bit)
access : read-write

TXE : Transmit FIFO empty.
bits : 1 - 2 (2 bit)
access : read-write

TXO : Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
bits : 2 - 4 (3 bit)
access : read-write

RXU : Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
bits : 3 - 6 (4 bit)
access : read-write

RXO : Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)
bits : 4 - 8 (5 bit)
access : read-write

RXF : Receive FIFO full
bits : 5 - 10 (6 bit)
access : read-write

DCMP : DMA Complete Interrupt
bits : 6 - 12 (7 bit)
access : read-write

DERR : DMA Error Interrupt
bits : 7 - 14 (8 bit)
access : read-write

CQCMP : Command Queue Complete Interrupt
bits : 8 - 16 (9 bit)
access : read-write

CQUPD : Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.
bits : 9 - 18 (10 bit)
access : read-write

CQPAUSED : Command Queue is Paused.
bits : 10 - 20 (11 bit)
access : read-write

CQERR : Command Queue Error Interrupt
bits : 11 - 22 (12 bit)
access : read-write

SCRERR : Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.
bits : 12 - 24 (13 bit)
access : read-write

CMDCMP : Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.
bits : 0 - 0 (1 bit)
access : read-write

TXE : Transmit FIFO empty.
bits : 1 - 2 (2 bit)
access : read-write

TXO : Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).
bits : 2 - 4 (3 bit)
access : read-write

RXU : Receive FIFO underflow (only occurs when SW reads from an empty FIFO)
bits : 3 - 6 (4 bit)
access : read-write

RXO : Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)
bits : 4 - 8 (5 bit)
access : read-write

RXF : Receive FIFO full
bits : 5 - 10 (6 bit)
access : read-write

DCMP : DMA Complete Interrupt
bits : 6 - 12 (7 bit)
access : read-write

DERR : DMA Error Interrupt
bits : 7 - 14 (8 bit)
access : read-write

CQCMP : Command Queue Complete Interrupt
bits : 8 - 16 (9 bit)
access : read-write

CQUPD : Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.
bits : 9 - 18 (10 bit)
access : read-write

CQPAUSED : Command Queue is Paused.
bits : 10 - 20 (11 bit)
access : read-write

CQERR : Command Queue Error Interrupt
bits : 11 - 22 (12 bit)
access : read-write

SCRERR : Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.
bits : 12 - 24 (13 bit)
access : read-write

DMAEN : DMA Enable. Setting this bit to EN will start the DMA operation
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMADIR : Direction
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAPRI : Sets the Priority of the DMA request
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAPWROFF : Power off MSPI domain upon completion of DMA operation.
bits : 18 - 36 (19 bit)
access : read-write

DMATIP : DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done.
bits : 0 - 0 (1 bit)
access : read-write

DMACPL : DMA Transfer Complete. This signals the end of the DMA operation.
bits : 1 - 2 (2 bit)
access : read-write

DMAERR : DMA Error. This active high bit signals that an error was encountered during the DMA operation.
bits : 2 - 4 (3 bit)
access : read-write

SCRERR : Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR.
bits : 3 - 6 (4 bit)
access : read-write

TARGADDR : Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
bits : 0 - 31 (32 bit)
access : read-write

DEVADDR : SPI Device address for automated DMA transactions (both read and write).
bits : 0 - 31 (32 bit)
access : read-write

TOTCOUNT : Total Transfer Count in bytes.
bits : 0 - 15 (16 bit)
access : read-write

BCOUNT : Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended values are 16 or 32.
bits : 0 - 7 (8 bit)
access : read-write

DMATHRESH : DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.
bits : 0 - 3 (4 bit)
access : read-write

CQEN : Command queue enable. When set, will enable the processing of the command queue
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQPRI : Sets the Priority of the command queue DMA request
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQPWROFF : Power off MSPI domain upon completion of DMA operation.
bits : 2 - 4 (3 bit)
access : read-write

CQAUTOCLEARMASK : Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ.
bits : 3 - 6 (4 bit)
access : read-write

CQADDR : Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary.
bits : 0 - 28 (29 bit)
access : read-write

CQTIP : Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.
bits : 0 - 0 (1 bit)
access : read-write

CQCPL : Command queue operation Complete. This signals the end of the command queue operation.
bits : 1 - 2 (2 bit)
access : read-write

CQERR : Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.
bits : 2 - 4 (3 bit)
access : read-write

CQPAUSED : Command queue is currently paused status.
bits : 3 - 6 (4 bit)
access : read-write

CQFLAGS : Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQFSET : Set CQFlag status bits. Set has priority over clear if both are high.
bits : 0 - 7 (8 bit)
access : read-write

CQFTOGGLE : Toggle CQFlag status bits
bits : 8 - 23 (16 bit)
access : read-write

CQFCLR : Clear CQFlag status bits.
bits : 16 - 39 (24 bit)
access : read-write

CQMASK : CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CQCURIDX : Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated.
bits : 0 - 7 (8 bit)
access : read-write

CQENDIDX : Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer.
bits : 0 - 7 (8 bit)
access : read-write

DEVCFG : Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format).
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASIZE : Address Size. Address bytes to send from ADDR register
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISIZE : Instruction Size enum name = I8 value = 0x0 desc = Instruction is 1 byte enum name = I16 value = 0x1 desc = Instruction is 2 bytes
bits : 6 - 12 (7 bit)
access : read-write

SEPIO : Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins.
bits : 7 - 14 (8 bit)
access : read-write

TURNAROUND : Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field.
bits : 8 - 21 (14 bit)
access : read-write

CPHA : Serial clock phase.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPOL : Serial clock polarity.
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR.
bits : 0 - 31 (32 bit)
access : read-write

INSTR : Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE
bits : 0 - 15 (16 bit)
access : read-write