\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
Voltage Regulator Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEBUCKEN : Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable the BLE Buck.
0 : DIS
Disable the BLE Buck.
End of enumeration elements list.
Enables individual banks of the MEMORY array
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCM : Power up DTCM
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
Do not enable power to any DTCMs
1 : GROUP0DTCM0
Power ON only GROUP0_DTCM0
2 : GROUP0DTCM1
Power ON only GROUP0_DTCM1
3 : GROUP0
Power ON only DTCMs in group0
4 : GROUP1
Power ON only DTCMs in group1
7 : ALL
Power ON all DTCMs
End of enumeration elements list.
SRAM : Power up SRAM groups
bits : 3 - 15 (13 bit)
access : read-write
Enumeration:
0 : NONE
Do not power ON any of the SRAM banks
1 : GROUP0
Power ON only SRAM group0 (0KB-32KB)
2 : GROUP1
Power ON only SRAM group1 (32KB-64KB)
4 : GROUP2
Power ON only SRAM group2 (64KB-96KB)
8 : GROUP3
Power ON only SRAM group3 (96KB-128KB)
16 : GROUP4
Power ON only SRAM group4 (128KB-160KB)
32 : GROUP5
Power ON only SRAM group5 (160KB-192KB)
64 : GROUP6
Power ON only SRAM group6 (192KB-224KB)
128 : GROUP7
Power ON only SRAM group7 (224KB-256KB)
256 : GROUP8
Power ON only SRAM group8 (256KB-288KB)
512 : GROUP9
Power ON only SRAM group9 (288KB-320KB)
3 : SRAM64K
Power ON only lower 64k
15 : SRAM128K
Power ON only lower 128k
255 : SRAM256K
Power ON only lower 256k
1023 : ALL
All SRAM banks (320K) powered ON
End of enumeration elements list.
FLASH0 : Power up Flash0
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
1 : EN
Power up Flash0
0 : DIS
Power down Flash0
End of enumeration elements list.
FLASH1 : Power up Flash1
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
1 : EN
Power up Flash1
0 : DIS
Power down Flash1
End of enumeration elements list.
CACHEB0 : Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank0, cache has to be enabled and this bit has to be set.
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
1 : EN
Power up Cache Bank 0
0 : DIS
Power down Cache Bank 0
End of enumeration elements list.
CACHEB2 : Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank2, cache has to be enabled and this bit has to be set.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Power up Cache Bank 2
0 : DIS
Power down Cache Bank 2
End of enumeration elements list.
Mem Power ON Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCM00 : This bit is 1 if power is supplied to DTCM GROUP0_0
bits : 0 - 0 (1 bit)
access : read-write
DTCM01 : This bit is 1 if power is supplied to DTCM GROUP0_1
bits : 1 - 2 (2 bit)
access : read-write
DTCM1 : This bit is 1 if power is supplied to DTCM GROUP1
bits : 2 - 4 (3 bit)
access : read-write
SRAM0 : This bit is 1 if power is supplied to SRAM GROUP0
bits : 3 - 6 (4 bit)
access : read-write
SRAM1 : This bit is 1 if power is supplied to SRAM GROUP1
bits : 4 - 8 (5 bit)
access : read-write
SRAM2 : This bit is 1 if power is supplied to SRAM GROUP2
bits : 5 - 10 (6 bit)
access : read-write
SRAM3 : This bit is 1 if power is supplied to SRAM GROUP3
bits : 6 - 12 (7 bit)
access : read-write
SRAM4 : This bit is 1 if power is supplied to SRAM GROUP4
bits : 7 - 14 (8 bit)
access : read-write
SRAM5 : This bit is 1 if power is supplied to SRAM GROUP5
bits : 8 - 16 (9 bit)
access : read-write
SRAM6 : This bit is 1 if power is supplied to SRAM GROUP6
bits : 9 - 18 (10 bit)
access : read-write
SRAM7 : This bit is 1 if power is supplied to SRAM GROUP7
bits : 10 - 20 (11 bit)
access : read-write
SRAM8 : This bit is 1 if power is supplied to SRAM GROUP8
bits : 11 - 22 (12 bit)
access : read-write
SRAM9 : This bit is 1 if power is supplied to SRAM GROUP9
bits : 12 - 24 (13 bit)
access : read-write
FLASH0 : This bit is 1 if power is supplied to FLASH 0
bits : 13 - 26 (14 bit)
access : read-write
FLASH1 : This bit is 1 if power is supplied to FLASH 1
bits : 14 - 28 (15 bit)
access : read-write
CACHEB0 : This bit is 1 if power is supplied to Cache Bank 0
bits : 15 - 30 (16 bit)
access : read-write
CACHEB2 : This bit is 1 if power is supplied to Cache Bank 2
bits : 16 - 32 (17 bit)
access : read-write
Device Power ON Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCUL : This bit is 1 if power is supplied to MCUL
bits : 0 - 0 (1 bit)
access : read-write
MCUH : This bit is 1 if power is supplied to MCUH
bits : 1 - 2 (2 bit)
access : read-write
HCPA : This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD)
bits : 2 - 4 (3 bit)
access : read-write
HCPB : This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2)
bits : 3 - 6 (4 bit)
access : read-write
HCPC : This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6)
bits : 4 - 8 (5 bit)
access : read-write
PWRADC : This bit is 1 if power is supplied to ADC
bits : 5 - 10 (6 bit)
access : read-write
PWRMSPI : This bit is 1 if power is supplied to MSPI
bits : 6 - 12 (7 bit)
access : read-write
PWRPDM : This bit is 1 if power is supplied to PDM
bits : 7 - 14 (8 bit)
access : read-write
BLEL : This bit is 1 if power is supplied to BLEL
bits : 8 - 16 (9 bit)
access : read-write
BLEH : This bit is 1 if power is supplied to BLEH
bits : 9 - 18 (10 bit)
access : read-write
SRAM Control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMCLKGATE : This bit is 1 if clock gating is allowed for individual system SRAMs
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable Individual SRAM Clock Gating
0 : DIS
Disables Individual SRAM Clock Gating
End of enumeration elements list.
SRAMMASTERCLKGATE : This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block)
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Enable Master SRAM Clock Gate
0 : DIS
Disables Master SRAM Clock Gating
End of enumeration elements list.
SRAMLIGHTSLEEP : Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses.
bits : 8 - 27 (20 bit)
access : read-write
Enumeration:
255 : ALL
Enable LIGHT SLEEP for ALL SRAMs
0 : DIS
Disables LIGHT SLEEP for ALL SRAMs
End of enumeration elements list.
Power Status Register for ADC Block
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCPWD : This bit indicates that the ADC is powered down
bits : 0 - 0 (1 bit)
access : read-write
BGTPWD : This bit indicates that the ADC Band Gap is powered down
bits : 1 - 2 (2 bit)
access : read-write
VPTATPWD : This bit indicates that the ADC temperature sensor input buffer is powered down
bits : 2 - 4 (3 bit)
access : read-write
VBATPWD : This bit indicates that the ADC VBAT resistor divider is powered down
bits : 3 - 6 (4 bit)
access : read-write
REFKEEPPWD : This bit indicates that the ADC REFKEEP is powered down
bits : 4 - 8 (5 bit)
access : read-write
REFBUFPWD : This bit indicates that the ADC REFBUF is powered down
bits : 5 - 10 (6 bit)
access : read-write
Power Optimization Control Bits
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEMEMVRLPTIMERS : Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running.
bits : 3 - 6 (4 bit)
access : read-write
MEMVRLPBLE : Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : EN
Mem VR can go to lp mode even when BLE is powered on.
0 : DIS
Mem VR will stay in active mode when BLE is powered on.
End of enumeration elements list.
Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCULEVEN : Control MCUL power-on status event
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Enable MCUL power-on status event
0 : DIS
Disable MCUL power-on status event
End of enumeration elements list.
MCUHEVEN : Control MCUH power-on status event
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Enable MCHU power-on status event
0 : DIS
Disable MCUH power-on status event
End of enumeration elements list.
HCPAEVEN : Control HCPA power-on status event
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Enable HCPA power-on status event
0 : DIS
Disable HCPA power-on status event
End of enumeration elements list.
HCPBEVEN : Control HCPB power-on status event
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : EN
Enable HCPB power-on status event
0 : DIS
Disable HCPB power-on status event
End of enumeration elements list.
HCPCEVEN : Control HCPC power-on status event
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : EN
Enable HCPC power-on status event
0 : DIS
Disable HCPC power-on status event
End of enumeration elements list.
ADCEVEN : Control ADC power-on status event
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : EN
Enable ADC power-on status event
0 : DIS
Disable ADC power-on status event
End of enumeration elements list.
MSPIEVEN : Control MSPI power-on status event
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : EN
Enable MSPI power-on status event
0 : DIS
Disable MSPI power-on status event
End of enumeration elements list.
PDMEVEN : Control PDM power-on status event
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : EN
Enable PDM power-on status event
0 : DIS
Disable PDM power-on status event
End of enumeration elements list.
BLELEVEN : Control BLE power-on status event
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : EN
Enable BLE power-on status event
0 : DIS
Disable BLE power-on status event
End of enumeration elements list.
BLEFEATUREEVEN : Control BLEFEATURE status event
bits : 29 - 58 (30 bit)
access : read-write
Enumeration:
1 : EN
Enable BLEFEATURE status event
0 : DIS
Disable BLEFEATURE status event
End of enumeration elements list.
BURSTFEATUREEVEN : Control BURSTFEATURE status event
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
1 : EN
Enable BURSTFEATURE status event
0 : DIS
Disable BURSTFEATURE status event
End of enumeration elements list.
BURSTEVEN : Control BURST status event
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Enable BURST status event
0 : DIS
Disable BURST status event
End of enumeration elements list.
Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCMEN : Enable DTCM power-on status event
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
Do not enable DTCM power-on status event
1 : GROUP0DTCM0EN
Enable GROUP0_DTCM0 power on status event
2 : GROUP0DTCM1EN
Enable GROUP0_DTCM1 power on status event
3 : GROUP0EN
Enable DTCMs in group0 power on status event
4 : GROUP1EN
Enable DTCMs in group1 power on status event
7 : ALL
Enable all DTCM power on status event
End of enumeration elements list.
SRAMEN : Control SRAM power-on status event
bits : 3 - 15 (13 bit)
access : read-write
Enumeration:
0 : NONE
Disable SRAM power-on status event
1 : GROUP0EN
Enable SRAM group0 (0KB-32KB) power on status event
2 : GROUP1EN
Enable SRAM group1 (32KB-64KB) power on status event
4 : GROUP2EN
Enable SRAM group2 (64KB-96KB) power on status event
8 : GROUP3EN
Enable SRAM group3 (96KB-128KB) power on status event
16 : GROUP4EN
Enable SRAM group4 (128KB-160KB) power on status event
32 : GROUP5EN
Enable SRAM group5 (160KB-192KB) power on status event
64 : GROUP6EN
Enable SRAM group6 (192KB-224KB) power on status event
128 : GROUP7EN
Enable SRAM group7 (224KB-256KB) power on status event
256 : GROUP8EN
Enable SRAM group8 (256KB-288KB) power on status event
512 : GROUP9EN
Enable SRAM group9 (288KB-320KB) power on status event
End of enumeration elements list.
FLASH0EN : Control Flash power-on status event
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
1 : EN
Enable FLASH status event
0 : DIS
Disables FLASH status event
End of enumeration elements list.
FLASH1EN : Control Flash power-on status event
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
1 : EN
Enable FLASH status event
0 : DIS
Disables FLASH status event
End of enumeration elements list.
CACHEB0EN : Control CACHE BANK 0 power-on status event
bits : 30 - 60 (31 bit)
access : read-write
Enumeration:
1 : EN
Enable CACHE BANK 0 status event
0 : DIS
Disable CACHE BANK 0 status event
End of enumeration elements list.
CACHEB2EN : Control CACHEB2 power-on status event
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Enable CACHE BANK 2 status event
0 : DIS
Disable CACHE BANK 2 status event
End of enumeration elements list.
Voltage Regulators status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIMOBUCKON : Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OFF
Indicates the the SIMO Buck is OFF.
1 : ON
Indicates the the SIMO Buck is ON.
End of enumeration elements list.
BLEBUCKON : Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate reature is allowed.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : LDO
Indicates the the LDO is supplying the BLE/Burst power domain
1 : BUCK
Indicates the the Buck is supplying the BLE/Burst power domain
End of enumeration elements list.
Device Power Enables
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRIOS : Power up IO Slave
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : EN
Power up IO slave
0 : DIS
Power down IO slave
End of enumeration elements list.
PWRIOM0 : Power up IO Master 0
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 0
0 : DIS
Power down IO Master 0
End of enumeration elements list.
PWRIOM1 : Power up IO Master 1
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 1
0 : DIS
Power down IO Master 1
End of enumeration elements list.
PWRIOM2 : Power up IO Master 2
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 2
0 : DIS
Power down IO Master 2
End of enumeration elements list.
PWRIOM3 : Power up IO Master 3
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 3
0 : DIS
Power down IO Master 3
End of enumeration elements list.
PWRIOM4 : Power up IO Master 4
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 4
0 : DIS
Power down IO Master 4
End of enumeration elements list.
PWRIOM5 : Power up IO Master 5
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : EN
Power up IO Master 5
0 : DIS
Power down IO Master 5
End of enumeration elements list.
PWRUART0 : Power up UART Controller 0
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : EN
Power up UART 0
0 : DIS
Power down UART 0
End of enumeration elements list.
PWRUART1 : Power up UART Controller 1
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
1 : EN
Power up UART 1
0 : DIS
Power down UART 1
End of enumeration elements list.
PWRADC : Power up ADC Digital Controller
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
1 : EN
Power up ADC
0 : DIS
Power Down ADC
End of enumeration elements list.
PWRSCARD : Power up SCARD Controller
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
1 : EN
Power up SCARD
0 : DIS
Power down SCARD
End of enumeration elements list.
PWRMSPI : Power up MSPI Controller
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
1 : EN
Power up MSPI
0 : DIS
Power down MSPI
End of enumeration elements list.
PWRPDM : Power up PDM block
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
1 : EN
Power up PDM
0 : DIS
Power down PDM
End of enumeration elements list.
PWRBLEL : Power up BLE controller
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
1 : EN
Power up BLE controller
0 : DIS
Power down BLE controller
End of enumeration elements list.
Powerdown SRAM banks in Deep Sleep mode
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCMPWDSLP : power down DTCM in deep sleep
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : NONE
All DTCM retained
1 : GROUP0DTCM0
Group0_DTCM0 powered down in deep sleep (0KB-8KB)
2 : GROUP0DTCM1
Group0_DTCM1 powered down in deep sleep (8KB-32KB)
3 : GROUP0
Both DTCMs in group0 are powered down in deep sleep (0KB-32KB)
6 : ALLBUTGROUP0DTCM0
Group1 and Group0_DTCM1 are powered down in deep sleep (8KB-64KB)
4 : GROUP1
Group1 DTCM powered down in deep sleep (32KB-64KB)
7 : ALL
All DTCMs powered down in deep sleep (0KB-64KB)
End of enumeration elements list.
SRAMPWDSLP : Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.
bits : 3 - 15 (13 bit)
access : read-write
Enumeration:
0 : NONE
All banks retained
1 : GROUP0
SRAM GROUP0 powered down (64KB-96KB)
2 : GROUP1
SRAM GROUP1 powered down (96KB-128KB)
4 : GROUP2
SRAM GROUP2 powered down (128KB-160KB)
8 : GROUP3
SRAM GROUP3 powered down (160KB-192KB)
16 : GROUP4
SRAM GROUP4 powered down (192KB-224KB)
32 : GROUP5
SRAM GROUP5 powered down (224KB-256KB)
64 : GROUP6
SRAM GROUP6 powered down (256KB-288KB)
128 : GROUP7
SRAM GROUP7 powered down (288KB-320KB)
256 : GROUP8
SRAM GROUP8 powered down (320KB-352KB)
512 : GROUP9
SRAM GROUP9 powered down (352KB-384KB)
3 : SRAM64K
Powerdown lower 64k SRAM (64KB-128KB)
15 : SRAM128K
Powerdown lower 128k SRAM (64KB-192KB)
1022 : ALLBUTLOWER32K
All SRAM banks but lower 32k powered down (96KB-384KB).
1020 : ALLBUTLOWER64K
All banks but lower 64k powered down.
1008 : ALLBUTLOWER128K
All banks but lower 128k powered down.
1023 : ALL
All banks powered down.
End of enumeration elements list.
FLASH0PWDSLP : Powerdown flash0 in deep sleep
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
1 : EN
Flash0 is powered down during deepsleep
0 : DIS
Flash0 is kept powered on during deepsleep
End of enumeration elements list.
FLASH1PWDSLP : Powerdown flash1 in deep sleep
bits : 14 - 28 (15 bit)
access : read-write
Enumeration:
1 : EN
Flash1 is powered down during deepsleep
0 : DIS
Flash1 is kept powered on during deepsleep
End of enumeration elements list.
CACHEPWDSLP : power down cache in deep sleep
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
1 : EN
Power down cache in deep sleep
0 : DIS
Retain cache in deep sleep
End of enumeration elements list.
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