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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection :

Registers

INTEN

INTSTAT

INTCLR

INTSET

CTRLOW

CTRUP

ALMLOW

ALMUP

RTCCTL


INTEN

RTC Interrupt Register: Enable
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM

ALM : RTC Alarm interrupt
bits : 0 - 0 (1 bit)
access : read-write


INTSTAT

RTC Interrupt Register: Status
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM

ALM : RTC Alarm interrupt
bits : 0 - 0 (1 bit)
access : read-write


INTCLR

RTC Interrupt Register: Clear
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM

ALM : RTC Alarm interrupt
bits : 0 - 0 (1 bit)
access : read-write


INTSET

RTC Interrupt Register: Set
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM

ALM : RTC Alarm interrupt
bits : 0 - 0 (1 bit)
access : read-write


CTRLOW

RTC Counters Lower
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLOW CTRLOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTR100 CTRSEC CTRMIN CTRHR

CTR100 : 100ths of a second Counter
bits : 0 - 7 (8 bit)
access : read-write

CTRSEC : Seconds Counter
bits : 8 - 22 (15 bit)
access : read-write

CTRMIN : Minutes Counter
bits : 16 - 38 (23 bit)
access : read-write

CTRHR : Hours Counter
bits : 24 - 53 (30 bit)
access : read-write


CTRUP

RTC Counters Upper
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRUP CTRUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRDATE CTRMO CTRYR CTRWKDY CB CEB CTERR

CTRDATE : Date Counter
bits : 0 - 5 (6 bit)
access : read-write

CTRMO : Months Counter
bits : 8 - 20 (13 bit)
access : read-write

CTRYR : Years Counter
bits : 16 - 39 (24 bit)
access : read-write

CTRWKDY : Weekdays Counter
bits : 24 - 50 (27 bit)
access : read-write

CB : Century
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

0 : 2000

Century is 2000s

1 : 1900_2100

Century is 1900s/2100s

End of enumeration elements list.

CEB : Century enable
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : DIS

Disable the Century bit from changing

1 : EN

Enable the Century bit to change

End of enumeration elements list.

CTERR : Counter read error status. Error is triggered when software reads the lower word of the counters, and fails to read the upper counter within 1/100 second. This is because when the lower counter is read, the upper counter is held off from incrementing until it is read so that the full time stamp can be read.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : NOERR

No read error occurred

1 : RDERR

Read error occurred

End of enumeration elements list.


ALMLOW

RTC Alarms Lower
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMLOW ALMLOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM100 ALMSEC ALMMIN ALMHR

ALM100 : 100ths of a second Alarm
bits : 0 - 7 (8 bit)
access : read-write

ALMSEC : Seconds Alarm
bits : 8 - 22 (15 bit)
access : read-write

ALMMIN : Minutes Alarm
bits : 16 - 38 (23 bit)
access : read-write

ALMHR : Hours Alarm
bits : 24 - 53 (30 bit)
access : read-write


ALMUP

RTC Alarms Upper
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMUP ALMUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMDATE ALMMO ALMWKDY

ALMDATE : Date Alarm
bits : 0 - 5 (6 bit)
access : read-write

ALMMO : Months Alarm
bits : 8 - 20 (13 bit)
access : read-write

ALMWKDY : Weekdays Alarm
bits : 16 - 34 (19 bit)
access : read-write


RTCCTL

RTC Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCCTL RTCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRTC RPT RSTOP HR1224

WRTC : Counter write control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Counter writes are disabled

1 : EN

Counter writes are enabled

End of enumeration elements list.

RPT : Alarm repeat interval
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0 : DIS

Alarm interrupt disabled

1 : YEAR

Interrupt every year

2 : MONTH

Interrupt every month

3 : WEEK

Interrupt every week

4 : DAY

Interrupt every day

5 : HR

Interrupt every hour

6 : MIN

Interrupt every minute

7 : SEC

Interrupt every second/10th/100th

End of enumeration elements list.

RSTOP : RTC input clock control
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : RUN

Allow the RTC input clock to run

1 : STOP

Stop the RTC input clock

End of enumeration elements list.

HR1224 : Hours Counter mode
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : 24HR

Hours in 24 hour mode

1 : 12HR

Hours in 12 hour mode

End of enumeration elements list.



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