\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection :
UART Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This is the UART data port.
bits : 0 - 7 (8 bit)
access : read-write
FEDATA : This is the framing error indicator.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART FEDATA, framing error indicator.
1 : ERR
Error on UART FEDATA, framing error indicator.
End of enumeration elements list.
PEDATA : This is the parity error indicator.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART PEDATA, parity error indicator.
1 : ERR
Error on UART PEDATA, parity error indicator.
End of enumeration elements list.
BEDATA : This is the break error indicator.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART BEDATA, break error indicator.
1 : ERR
Error on UART BEDATA, break error indicator.
End of enumeration elements list.
OEDATA : This is the overrun error indicator.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART OEDATA, overrun error indicator.
1 : ERR
Error on UART OEDATA, overrun error indicator.
End of enumeration elements list.
Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTS : This bit holds the clear to send indicator.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : CLEARTOSEND
Clear to send is indicated.
End of enumeration elements list.
DSR : This bit holds the data set ready indicator.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : READY
Data set ready.
End of enumeration elements list.
DCD : This bit holds the data carrier detect indicator.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : DETECTED
Data carrier detect detected.
End of enumeration elements list.
BUSY : This bit holds the busy indicator.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
1 : BUSY
UART busy indicator.
End of enumeration elements list.
RXFE : This bit holds the receive FIFO empty indicator.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
1 : RCVFIFO_EMPTY
Receive fifo is empty.
End of enumeration elements list.
TXFF : This bit holds the transmit FIFO full indicator.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
1 : XMTFIFO_FULL
Transmit fifo is full.
End of enumeration elements list.
RXFF : This bit holds the receive FIFO full indicator.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
1 : RCVFIFO_FULL
Receive fifo is full.
End of enumeration elements list.
TXFE : This bit holds the transmit FIFO empty indicator.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
1 : XMTFIFO_EMPTY
Transmit fifo is empty.
End of enumeration elements list.
TXBUSY : This bit holds the transmit BUSY indicator.
bits : 8 - 16 (9 bit)
access : read-write
IrDA Counter
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILPDVSR : These bits hold the IrDA counter divisor.
bits : 0 - 7 (8 bit)
access : read-write
Integer Baud Rate Divisor
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVINT : These bits hold the baud integer divisor.
bits : 0 - 15 (16 bit)
access : read-write
Fractional Baud Rate Divisor
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVFRAC : These bits hold the baud fractional divisor.
bits : 0 - 5 (6 bit)
access : read-write
Line Control High
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : This bit holds the break set.
bits : 0 - 0 (1 bit)
access : read-write
PEN : This bit holds the parity enable.
bits : 1 - 2 (2 bit)
access : read-write
EPS : This bit holds the even parity select.
bits : 2 - 4 (3 bit)
access : read-write
STP2 : This bit holds the two stop bits select.
bits : 3 - 6 (4 bit)
access : read-write
FEN : This bit holds the FIFO enable.
bits : 4 - 8 (5 bit)
access : read-write
WLEN : These bits hold the write length.
bits : 5 - 11 (7 bit)
access : read-write
SPS : This bit holds the stick parity select.
bits : 7 - 14 (8 bit)
access : read-write
Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : This bit is the UART enable.
bits : 0 - 0 (1 bit)
access : read-write
SIREN : This bit is the SIR ENDEC enable.
bits : 1 - 2 (2 bit)
access : read-write
SIRLP : This bit is the SIR low power select.
bits : 2 - 4 (3 bit)
access : read-write
CLKEN : This bit is the UART clock enable.
bits : 3 - 6 (4 bit)
access : read-write
CLKSEL : This bitfield is the UART clock select.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : NOCLK
No UART clock. This is the low power default.
1 : 24MHZ
24 MHz clock.
2 : 12MHZ
12 MHz clock.
3 : 6MHZ
6 MHz clock.
4 : 3MHZ
3 MHz clock.
End of enumeration elements list.
LBE : This bit is the loopback enable.
bits : 7 - 14 (8 bit)
access : read-write
TXE : This bit is the transmit enable.
bits : 8 - 16 (9 bit)
access : read-write
RXE : This bit is the receive enable.
bits : 9 - 18 (10 bit)
access : read-write
DTR : This bit enables data transmit ready.
bits : 10 - 20 (11 bit)
access : read-write
RTS : This bit enables request to send.
bits : 11 - 22 (12 bit)
access : read-write
OUT1 : This bit holds modem Out1.
bits : 12 - 24 (13 bit)
access : read-write
OUT2 : This bit holds modem Out2.
bits : 13 - 26 (14 bit)
access : read-write
RTSEN : This bit enables RTS hardware flow control.
bits : 14 - 28 (15 bit)
access : read-write
CTSEN : This bit enables CTS hardware flow control.
bits : 15 - 30 (16 bit)
access : read-write
FIFO Interrupt Level Select
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXIFLSEL : These bits hold the transmit FIFO interrupt level.
bits : 0 - 2 (3 bit)
access : read-write
RXIFLSEL : These bits hold the receive FIFO interrupt level.
bits : 3 - 8 (6 bit)
access : read-write
Interrupt Enable
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCMPMIM : This bit holds the modem TXCMP interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write
CTSMIM : This bit holds the modem CTS interrupt enable.
bits : 1 - 2 (2 bit)
access : read-write
DCDMIM : This bit holds the modem DCD interrupt enable.
bits : 2 - 4 (3 bit)
access : read-write
DSRMIM : This bit holds the modem DSR interrupt enable.
bits : 3 - 6 (4 bit)
access : read-write
RXIM : This bit holds the receive interrupt enable.
bits : 4 - 8 (5 bit)
access : read-write
TXIM : This bit holds the transmit interrupt enable.
bits : 5 - 10 (6 bit)
access : read-write
RTIM : This bit holds the receive timeout interrupt enable.
bits : 6 - 12 (7 bit)
access : read-write
FEIM : This bit holds the framing error interrupt enable.
bits : 7 - 14 (8 bit)
access : read-write
PEIM : This bit holds the parity error interrupt enable.
bits : 8 - 16 (9 bit)
access : read-write
BEIM : This bit holds the break error interrupt enable.
bits : 9 - 18 (10 bit)
access : read-write
OEIM : This bit holds the overflow interrupt enable.
bits : 10 - 20 (11 bit)
access : read-write
Interrupt Status
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCMPMRIS : This bit holds the modem TXCMP interrupt status.
bits : 0 - 0 (1 bit)
access : read-write
CTSMRIS : This bit holds the modem CTS interrupt status.
bits : 1 - 2 (2 bit)
access : read-write
DCDMRIS : This bit holds the modem DCD interrupt status.
bits : 2 - 4 (3 bit)
access : read-write
DSRMRIS : This bit holds the modem DSR interrupt status.
bits : 3 - 6 (4 bit)
access : read-write
RXRIS : This bit holds the receive interrupt status.
bits : 4 - 8 (5 bit)
access : read-write
TXRIS : This bit holds the transmit interrupt status.
bits : 5 - 10 (6 bit)
access : read-write
RTRIS : This bit holds the receive timeout interrupt status.
bits : 6 - 12 (7 bit)
access : read-write
FERIS : This bit holds the framing error interrupt status.
bits : 7 - 14 (8 bit)
access : read-write
PERIS : This bit holds the parity error interrupt status.
bits : 8 - 16 (9 bit)
access : read-write
BERIS : This bit holds the break error interrupt status.
bits : 9 - 18 (10 bit)
access : read-write
OERIS : This bit holds the overflow interrupt status.
bits : 10 - 20 (11 bit)
access : read-write
UART Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FESTAT : This is the framing error indicator.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART FESTAT, framing error indicator.
1 : ERR
Error on UART FESTAT, framing error indicator.
End of enumeration elements list.
PESTAT : This is the parity error indicator.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART PESTAT, parity error indicator.
1 : ERR
Error on UART PESTAT, parity error indicator.
End of enumeration elements list.
BESTAT : This is the break error indicator.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART BESTAT, break error indicator.
1 : ERR
Error on UART BESTAT, break error indicator.
End of enumeration elements list.
OESTAT : This is the overrun error indicator.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : NOERR
No error on UART OESTAT, overrun error indicator.
1 : ERR
Error on UART OESTAT, overrun error indicator.
End of enumeration elements list.
Masked Interrupt Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCMPMMIS : This bit holds the modem TXCMP interrupt status masked.
bits : 0 - 0 (1 bit)
access : read-write
CTSMMIS : This bit holds the modem CTS interrupt status masked.
bits : 1 - 2 (2 bit)
access : read-write
DCDMMIS : This bit holds the modem DCD interrupt status masked.
bits : 2 - 4 (3 bit)
access : read-write
DSRMMIS : This bit holds the modem DSR interrupt status masked.
bits : 3 - 6 (4 bit)
access : read-write
RXMIS : This bit holds the receive interrupt status masked.
bits : 4 - 8 (5 bit)
access : read-write
TXMIS : This bit holds the transmit interrupt status masked.
bits : 5 - 10 (6 bit)
access : read-write
RTMIS : This bit holds the receive timeout interrupt status masked.
bits : 6 - 12 (7 bit)
access : read-write
FEMIS : This bit holds the framing error interrupt status masked.
bits : 7 - 14 (8 bit)
access : read-write
PEMIS : This bit holds the parity error interrupt status masked.
bits : 8 - 16 (9 bit)
access : read-write
BEMIS : This bit holds the break error interrupt status masked.
bits : 9 - 18 (10 bit)
access : read-write
OEMIS : This bit holds the overflow interrupt status masked.
bits : 10 - 20 (11 bit)
access : read-write
Interrupt Clear
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCMPMIC : This bit holds the modem TXCMP interrupt clear.
bits : 0 - 0 (1 bit)
access : read-write
CTSMIC : This bit holds the modem CTS interrupt clear.
bits : 1 - 2 (2 bit)
access : read-write
DCDMIC : This bit holds the modem DCD interrupt clear.
bits : 2 - 4 (3 bit)
access : read-write
DSRMIC : This bit holds the modem DSR interrupt clear.
bits : 3 - 6 (4 bit)
access : read-write
RXIC : This bit holds the receive interrupt clear.
bits : 4 - 8 (5 bit)
access : read-write
TXIC : This bit holds the transmit interrupt clear.
bits : 5 - 10 (6 bit)
access : read-write
RTIC : This bit holds the receive timeout interrupt clear.
bits : 6 - 12 (7 bit)
access : read-write
FEIC : This bit holds the framing error interrupt clear.
bits : 7 - 14 (8 bit)
access : read-write
PEIC : This bit holds the parity error interrupt clear.
bits : 8 - 16 (9 bit)
access : read-write
BEIC : This bit holds the break error interrupt clear.
bits : 9 - 18 (10 bit)
access : read-write
OEIC : This bit holds the overflow interrupt clear.
bits : 10 - 20 (11 bit)
access : read-write
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