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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x210 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

INTEN

INTSTAT

INTCLR

INTSET

RSTRT

LOCK

COUNT


CFG

Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTEN INTEN RESEN RESVAL INTVAL CLKSEL

WDTEN : This bitfield enables the WDT.
bits : 0 - 0 (1 bit)
access : read-write

INTEN : This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.
bits : 1 - 2 (2 bit)
access : read-write

RESEN : This bitfield enables the WDT reset. This needs to be set together with the WDREN bit in REG_RSTGEN_CFG register (in reset gen) to trigger the reset.
bits : 2 - 4 (3 bit)
access : read-write

RESVAL : This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset.
bits : 8 - 23 (16 bit)
access : read-write

INTVAL : This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt.
bits : 16 - 39 (24 bit)
access : read-write

CLKSEL : Select the frequency for the WDT. All values not enumerated below are undefined.
bits : 24 - 50 (27 bit)
access : read-write

Enumeration:

0 : OFF

Low Power Mode. This setting disables the watch dog timer.

1 : 128HZ

128 Hz LFRC clock.

2 : 16HZ

16 Hz LFRC clock.

3 : 1HZ

1 Hz LFRC clock.

4 : 1_16HZ

1/16th Hz LFRC clock.

End of enumeration elements list.


INTEN

WDT Interrupt register: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTINT

WDTINT : Watchdog Timer Interrupt.
bits : 0 - 0 (1 bit)
access : read-write


INTSTAT

WDT Interrupt register: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTINT

WDTINT : Watchdog Timer Interrupt.
bits : 0 - 0 (1 bit)
access : read-write


INTCLR

WDT Interrupt register: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTINT

WDTINT : Watchdog Timer Interrupt.
bits : 0 - 0 (1 bit)
access : read-write


INTSET

WDT Interrupt register: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTINT

WDTINT : Watchdog Timer Interrupt.
bits : 0 - 0 (1 bit)
access : read-write


RSTRT

Restart the watchdog timer.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTRT RSTRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRT

RSTRT : Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

178 : KEYVALUE

This is the key value to write to WDTRSTRT to restart the WDT. This is a write only register.

End of enumeration elements list.


LOCK

Locks the WDT
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

58 : KEYVALUE

This is the key value to write to WDTLOCK to lock the WDT.

End of enumeration elements list.


COUNT

Current Counter Value for WDT
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Read-Only current value of the WDT counter
bits : 0 - 7 (8 bit)
access : read-write



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