\n
address_offset : 0x0 Bytes (0x0)
size : 0x414 byte (0x0)
mem_usage : registers
protection :
FIFO Access Port
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO direct access. Only locations 0 - 3F will return valid information.
bits : 0 - 31 (32 bit)
access : read-write
FIFO size and remaining slots open values
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO0SIZ : The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)
bits : 0 - 7 (8 bit)
access : read-write
FIFO0REM : The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)
bits : 8 - 23 (16 bit)
access : read-write
FIFO1SIZ : The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)
bits : 16 - 39 (24 bit)
access : read-write
FIFO1REM : The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)
bits : 24 - 55 (32 bit)
access : read-write
FIFO Threshold Configuration
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFORTHR : FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read FIFO to support large IOM read operations.
bits : 0 - 5 (6 bit)
access : read-write
FIFOWTHR : FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write FIFO to support large IOM write operations.
bits : 8 - 21 (14 bit)
access : read-write
FIFO POP register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFODOUT : This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the FIFO read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the FIFO read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.
bits : 0 - 31 (32 bit)
access : read-write
FIFO PUSH register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFODIN : This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).
bits : 0 - 31 (32 bit)
access : read-write
FIFO Control
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POPWR : Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertent FIFO pops when used in a debugging mode.
bits : 0 - 0 (1 bit)
access : read-write
FIFORSTN : Active low manual reset of the FIFO. Write to 0 to reset FIFO, and then write to 1 to remove the reset.
bits : 1 - 2 (2 bit)
access : read-write
FIFO Pointers
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOWPTR : Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.
bits : 0 - 3 (4 bit)
access : read-write
FIFORPTR : Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.
bits : 8 - 19 (12 bit)
access : read-write
IO Master Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command complete interrupt
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write
STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write
ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write
CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write
CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write
IO Master Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command complete interrupt
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write
STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write
ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write
CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write
CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write
IO Master Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command complete interrupt
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write
STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write
ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write
CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write
CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write
IO Master Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDCMP : Command complete interrupt
bits : 0 - 0 (1 bit)
access : read-write
THR : FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.
bits : 1 - 2 (2 bit)
access : read-write
FUNDFL : Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.
bits : 2 - 4 (3 bit)
access : read-write
FOVFL : Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.
bits : 3 - 6 (4 bit)
access : read-write
NAK : I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.
bits : 4 - 8 (5 bit)
access : read-write
IACC : illegal FIFO access interrupt. Asserted when there is a overflow or underflow event
bits : 5 - 10 (6 bit)
access : read-write
ICMD : illegal command interrupt. Asserted when a command is written when an active command is in progress.
bits : 6 - 12 (7 bit)
access : read-write
START : START command interrupt. Asserted when another master on the bus has signaled a START command.
bits : 7 - 14 (8 bit)
access : read-write
STOP : STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.
bits : 8 - 16 (9 bit)
access : read-write
ARB : Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.
bits : 9 - 18 (10 bit)
access : read-write
DCMP : DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state
bits : 10 - 20 (11 bit)
access : read-write
DERR : DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.
bits : 11 - 22 (12 bit)
access : read-write
CQPAUSED : Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.
bits : 12 - 24 (13 bit)
access : read-write
CQUPD : CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.
bits : 13 - 26 (14 bit)
access : read-write
CQERR : Error during command queue operations
bits : 14 - 28 (15 bit)
access : read-write
I/O Clock Configuration
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOCLKEN : Enable for the interface clock. Must be enabled prior to executing any IO operations.
bits : 0 - 0 (1 bit)
access : read-write
FSEL : Select the input clock frequency.
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : MIN_PWR
Selects the minimum power clock. This setting should be used whenever the IOM is not active.
1 : HFRC
Selects the HFRC as the input clock.
2 : HFRC_DIV2
Selects the HFRC / 2 as the input clock.
3 : HFRC_DIV4
Selects the HFRC / 4 as the input clock.
4 : HFRC_DIV8
Selects the HFRC / 8 as the input clock.
5 : HFRC_DIV16
Selects the HFRC / 16 as the input clock.
6 : HFRC_DIV32
Selects the HFRC / 32 as the input clock.
7 : HFRC_DIV64
Selects the HFRC / 64 as the input clock.
End of enumeration elements list.
DIV3 : Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled will provide the divided by 3 clock as the source to the programmable divider.
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
0 : DIS
Select divide by 1.
1 : EN
Select divide by 3.
End of enumeration elements list.
DIVEN : Enable clock division by TOTPER and LOWPER
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : DIS
Disable TOTPER division.
1 : EN
Enable TOTPER division.
End of enumeration elements list.
LOWPER : Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1. Only applicable when DIVEN = 1.
bits : 16 - 39 (24 bit)
access : read-write
TOTPER : Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The source clock is selected by FSEL. Only applicable when DIVEN = 1.
bits : 24 - 55 (32 bit)
access : read-write
Submodule control
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD0EN : Submodule 0 enable (1) or disable (0)
bits : 0 - 0 (1 bit)
access : read-write
SMOD0TYPE : Submodule 0 module type. This is the SPI Master interface.
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0 : SPI_MASTER
MSPI submodule
1 : I2C_MASTER
I2C Master submodule
2 : SSPI
SPI Slave submodule
3 : SI2C
I2C Slave submodule
7 : NA
NOT INSTALLED
End of enumeration elements list.
SMOD1EN : Submodule 1 enable (1) or disable (0)
bits : 4 - 8 (5 bit)
access : read-write
SMOD1TYPE : Submodule 0 module type. This is the I2C Master interface
bits : 5 - 12 (8 bit)
access : read-write
Enumeration:
0 : MSPI
SPI Master submodule
1 : I2C_MASTER
MI2C submodule
2 : SSPI
SPI Slave submodule
3 : SI2C
I2C Slave submodule
7 : NA
NOT INSTALLED
End of enumeration elements list.
Command and Offset
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Command for submodule.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
1 : WRITE
Write command using count of offset bytes specified in the OFFSETCNT field
2 : READ
Read command using count of offset bytes specified in the OFFSETCNT field
3 : TMW
SPI only. Test mode to do constant write operations. Useful for debug and power measurements. Will continually send data in OFFSET field
4 : TMR
SPI Only. Test mode to do constant read operations. Useful for debug and power measurements. Will continually read data from external input
End of enumeration elements list.
OFFSETCNT : Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If OFFSETCNT == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.
bits : 5 - 11 (7 bit)
access : read-write
CONT : Continue to hold the bus after the current transaction if set to a 1 with a new command issued.
bits : 7 - 14 (8 bit)
access : read-write
TSIZE : Defines the transaction size in bytes. The offset transfer is not included in this size.
bits : 8 - 27 (20 bit)
access : read-write
CMDSEL : Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions
bits : 20 - 41 (22 bit)
access : read-write
OFFSETLO : This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command.
bits : 24 - 55 (32 bit)
access : read-write
DCX Control
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CE0OUT : Enable DCX output using CE0 output
bits : 0 - 0 (1 bit)
access : read-write
CE1OUT : Enable DCX output using CE1 output
bits : 1 - 2 (2 bit)
access : read-write
CE2OUT : Enable DCX output using CE2 output
bits : 2 - 4 (3 bit)
access : read-write
CE3OUT : Enable DCX output using CE3 output
bits : 3 - 6 (4 bit)
access : read-write
DCXEN : DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte, and high during transmission of data bytes.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
16 : EN
Enable DCX.
0 : DIS
Disable DCX.
End of enumeration elements list.
High order 2 bytes of 3 byte offset for IO transaction
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETHI : Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register
bits : 0 - 15 (16 bit)
access : read-write
Command status
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCMD : current command that is being executed
bits : 0 - 4 (5 bit)
access : read-write
CMDSTAT : The current status of the command execution.
bits : 5 - 12 (8 bit)
access : read-write
Enumeration:
1 : ERR
Error encountered with command
2 : ACTIVE
Actively processing command
4 : IDLE
Idle state, no active command, no error
6 : WAIT
Command in progress, but waiting on data from host
End of enumeration elements list.
CTSIZE : The current number of bytes still to be transferred with this command. This field will count down to zero.
bits : 8 - 27 (20 bit)
access : read-write
DMA Trigger Enable
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMDCMPEN : Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or
bits : 0 - 0 (1 bit)
access : read-write
DTHREN : Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the FIFO, since the RTHR has not been reached. In this case, the CMDCMP trigger must also be enabled to transfer the remaining read FIFO data to SRAM.
bits : 1 - 2 (2 bit)
access : read-write
DMA Trigger Status
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMDCMP : Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.
bits : 0 - 0 (1 bit)
access : read-write
DTHR : Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 1 - 2 (2 bit)
access : read-write
DTOTCMP : DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.
bits : 2 - 4 (3 bit)
access : read-write
DMA Configuration
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable DMA Function
1 : EN
Enable DMA Function
End of enumeration elements list.
DMADIR : Direction
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : P2M
Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, i.e., reading data from external devices.
1 : M2P
Memory to Peripheral transaction. To be set when doing IOM write operations, i.e., writing data to external devices.
End of enumeration elements list.
DMAPRI : Sets the Priority of the DMA request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : LOW
Low Priority (service as best effort)
1 : HIGH
High Priority (service immediately)
End of enumeration elements list.
DPWROFF : Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DIS
Power off disabled
1 : EN
Power off enabled
End of enumeration elements list.
DMA Total Transfer Count
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOTCOUNT : Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.
bits : 0 - 11 (12 bit)
access : read-write
DMA Target Address
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TARGADDR : Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
bits : 0 - 20 (21 bit)
access : read-write
TARGADDR28 : Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash
bits : 28 - 56 (29 bit)
access : read-write
DMA Status
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMATIP : DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write
DMACPL : DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0, and will also be cleared when a new DMA is started.
bits : 1 - 2 (2 bit)
access : read-write
DMAERR : DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set, this bit will remain set until cleared by software.
bits : 2 - 4 (3 bit)
access : read-write
Command Queue Configuration
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQEN : Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable CQ Function
1 : EN
Enable CQ Function
End of enumeration elements list.
CQPRI : Sets the Priority of the command queue DMA request
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : LOW
Low Priority (service as best effort)
1 : HIGH
High Priority (service immediately)
End of enumeration elements list.
MSPIFLGSEL : Selects the MPSI modules used for sourcing the CQFLAG [11:8].
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : MSPI0FLGSEL
Selects MPSI0 as source of signals used in CGFLAG[11:8].
1 : MSPI1FLGSEL
Selects MPSI1 as source of signals used in CGFLAG[11:8].
2 : MSPI2FLGSEL
Selects MPSI2 as source of signals used in CGFLAG[11:8].
End of enumeration elements list.
CQ Target Read Address
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQADDR : Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary
bits : 2 - 22 (21 bit)
access : read-write
CQADDR28 : Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access
bits : 28 - 56 (29 bit)
access : read-write
Command Queue Status
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQTIP : Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.
bits : 0 - 0 (1 bit)
access : read-write
CQPAUSED : Command queue operation is currently paused.
bits : 1 - 2 (2 bit)
access : read-write
CQERR : Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.
bits : 2 - 4 (3 bit)
access : read-write
Command Queue Flag
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQFLAGS : Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.
bits : 0 - 15 (16 bit)
access : read-write
CQIRQMASK : Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE
bits : 16 - 47 (32 bit)
access : read-write
Command Queue Flag Set/Clear
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQFSET : Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 0 - 7 (8 bit)
access : read-write
CQFTGL : Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field
bits : 8 - 23 (16 bit)
access : read-write
CQFCLR : Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field
bits : 16 - 39 (24 bit)
access : read-write
Command Queue Pause Enable
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQPEN : Enables the specified event to pause command processing when active
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
32768 : IDXEQ
Pauses the command queue when the current index matches the last index
16384 : BLEXOREN
Pause command queue when input BLE bit XORed with SWFLAG4 is '1'
8192 : IOMXOREN
Pause command queue when input IOM bit XORed with SWFLAG3 is '1'
4096 : GPIOXOREN
Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1'
2048 : MSPI1XNOREN
Pause command queue when selected MSPI input bit 1 (buffer 1 ready) XNORed with SWFLAG1 is '1'. MSPI used is selected in CQCFG.MSPIFLGSEL field.
1024 : MSPI0XNOREN
Pause command queue when selected MSPI input bit 0 (buffer 0 ready) XNORed with SWFLAG1 is '1'. MSPI used is selected in CQCFG.MSPIFLGSEL field.
512 : MSPI1XOREN
Pause command queue when selected MSPI input bit 1 (buffer 1 ready) XORed with SWFLAG1 is '1'. MSPI used is selected in CQCFG.MSPIFLGSEL field.
256 : MSPI0XOREN
Pause command queue when selected MSPI input bit 0 (buffer 0 ready) XORed with SWFLAG1 is '1'. MSPI used is selected in CQCFG.MSPIFLGSEL field.
128 : SWFLAGEN7
Pause the command queue when software flag bit 7 is '1'.
64 : SWFLAGEN6
Pause the command queue when software flag bit 6 is '1'
32 : SWFLAGEN5
Pause the command queue when software flag bit 5 is '1'
16 : SWFLAGEN4
Pause the command queue when software flag bit 4 is '1'
8 : SWFLAGEN3
Pause the command queue when software flag bit 3 is '1'
4 : SWFLAGEN2
Pause the command queue when software flag bit 2 is '1'
2 : SWFLAGEN1
Pause the command queue when software flag bit 1 is '1'
1 : SWFLAGEN0
Pause the command queue when software flag bit 0 is '1'
End of enumeration elements list.
IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQCURIDX : Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write
IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQENDIDX : Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.
bits : 0 - 7 (8 bit)
access : read-write
IOM Module Status
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : Bit has been deprecated. Please refer to the other error indicators. This will always return 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
1 : ERROR
Bit has been deprecated and will always return 0.
End of enumeration elements list.
CMDACT : Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still synchronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been synchronized.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
1 : ACTIVE
An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed.
End of enumeration elements list.
IDLEST : indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability, or as the command gets propagated into the logic from the registers.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : IDLE
The I/O state machine is in the idle state.
End of enumeration elements list.
SPI module master configuration
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOL : selects SPI polarity.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CLK_BASE_0
The base value of the clock is 0.
1 : CLK_BASE_1
The base value of the clock is 1.
End of enumeration elements list.
SPHA : selects SPI phase.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : SAMPLE_LEADING_EDGE
Sample on the leading (first) clock edge.
1 : SAMPLE_TRAILING_EDGE
Sample on the trailing (second) clock edge.
End of enumeration elements list.
FULLDUP : Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO
bits : 2 - 4 (3 bit)
access : read-write
WTFC : enables write mode flow control.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : DIS
Write mode flow control disabled.
1 : EN
Write mode flow control enabled.
End of enumeration elements list.
RDFC : enables read mode flow control.
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
0 : DIS
Read mode flow control disabled.
1 : EN
Read mode flow control enabled.
End of enumeration elements list.
MOSIINV : inverts MOSI when flow control is enabled.
bits : 18 - 36 (19 bit)
access : read-write
Enumeration:
0 : NORMAL
MOSI is set to 0 in read mode and 1 in write mode.
1 : INVERT
MOSI is set to 1 in read mode and 0 in write mode.
End of enumeration elements list.
WTFCIRQ : selects the write mode flow control signal.
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
0 : MISO
MISO is used as the write mode flow control signal.
1 : IRQ
IRQ is used as the write mode flow control signal.
End of enumeration elements list.
WTFCPOL : selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers).
bits : 21 - 42 (22 bit)
access : read-write
Enumeration:
0 : HIGH
Flow control signal high(1) creates flow control and byte transfers will stop until the flow control signal goes low.
1 : LOW
Flow control signal low(0) creates flow control and byte transfers will stop until the flow control signal goes high(1).
End of enumeration elements list.
RDFCPOL : selects the read flow control signal polarity.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : HIGH
Flow control signal high creates flow control.
1 : LOW
Flow control signal low creates flow control.
End of enumeration elements list.
SPILSB : Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.
bits : 23 - 46 (24 bit)
access : read-write
Enumeration:
0 : MSB
Send and receive MSB bit first
1 : LSB
Send and receive LSB bit first
End of enumeration elements list.
DINDLY : Delay tap to use for the input signal (MISO). This gives more hold time on the input data.
bits : 24 - 50 (27 bit)
access : read-write
DOUTDLY : Delay tap to use for the output signal (MOSI). This give more hold time on the output data
bits : 27 - 56 (30 bit)
access : read-write
MSPIRST : Not used. To reset the module, toggle the SMOD_EN for the module
bits : 30 - 60 (31 bit)
access : read-write
I2C Master configuration
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRSZ : Sets the I2C master device address size to either 7 bits (0) or 10 bits (1).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ADDRSZ7
Use 7-bit addressing for I2C master transactions
1 : ADDRSZ10
Use 10-bit addressing for I2C master transactions
End of enumeration elements list.
I2CLSB : Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : MSBFIRST
Byte data is transmitted MSB first onto the bus/read from the bus
1 : LSBFIRST
Byte data is transmitted LSB first onto the bus/read from the bus
End of enumeration elements list.
ARBEN : Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
1 : ARBEN
Enable multi-master bus arbitration support for this I2C master
0 : ARBDIS
Disable multi-master bus arbitration support for this I2C master
End of enumeration elements list.
SDADLY : Delay to enable on the SDA output. Values are 0x0-0x3.
bits : 4 - 9 (6 bit)
access : read-write
MI2CRST : Not used. To reset the module, toggle the SMOD_EN for the module
bits : 6 - 12 (7 bit)
access : read-write
SCLENDLY : Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping.
bits : 8 - 19 (12 bit)
access : read-write
SDAENDLY : Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock
bits : 12 - 27 (16 bit)
access : read-write
SMPCNT : Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred
bits : 16 - 39 (24 bit)
access : read-write
STRDIS : Disable detection of clock stretch events smaller than 1 cycle
bits : 24 - 48 (25 bit)
access : read-write
I2C Device Configuration register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVADDR : I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address.
bits : 0 - 9 (10 bit)
access : read-write
IOM Debug
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGEN : Debug Enable. Setting bit will enable the update of data within this register, otherwise it is clock gated for power savings
bits : 0 - 0 (1 bit)
access : read-write
IOCLKON : IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 1 - 2 (2 bit)
access : read-write
APBCLKON : APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.
bits : 2 - 4 (3 bit)
access : read-write
DBGDATA : Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers.
bits : 3 - 34 (32 bit)
access : read-write
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