CHIPPN

VENDORID

ADCPWRDLY

ADCCAL

ADCBATTLOAD

ADCTRIM

ADCREFCOMP

XTALCTRL

XTALGENCTRL

SKU

FEATUREENABLE

MISCCTRL

BOOTLOADER

SHADOWVALID

SCRATCH0

SCRATCH1

ICODEFAULTADDR

DCODEFAULTADDR

SYSFAULTADDR

FAULTSTATUS

FAULTCAPTUREEN

DEBUGGER

DBGR1

DBGR2

PMUENABLE

TPIUCTRL

OTAPOINTER

SRAMMODE

KEXTCLKSEL

SIMOBUCK2

SIMOBUCK3

SIMOBUCK4

BLEBUCK2

DMASRAMWRITEPROTECT2

FLASHWPROT0

FLASHWPROT1

FLASHWPROT2

FLASHWPROT3

FLASHRPROT0

FLASHRPROT1

FLASHRPROT2

FLASHRPROT3

DMASRAMWRITEPROTECT0

DMASRAMWRITEPROTECT1

DMASRAMREADPROTECT0

DMASRAMREADPROTECT1

DMASRAMREADPROTECT2

CHIPID0

CHIPID1

CHIPREV

PARTNUM : BCD part number.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VENDORID : Unique Vendor ID
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCPWR0 : ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.
bits : 0 - 7 (8 bit)
access : read-write

ADCPWR1 : ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.
bits : 8 - 23 (16 bit)
access : read-write

CALONPWRUP : Run ADC Calibration on initial power up sequence
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCCALIBRATED : Status for ADC Calibration
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BATTLOAD : Enable the ADC battery load resistor
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCREFKEEPIBTRIM : ADC Reference Ibias trim
bits : 0 - 1 (2 bit)
access : read-write

ADCREFBUFTRIM : ADC Reference buffer trim
bits : 6 - 16 (11 bit)
access : read-write

ADCRFBUFIBTRIM : ADC reference buffer input bias trim
bits : 11 - 23 (13 bit)
access : read-write

ADC_REFCOMP_OUT : Output of the ADC reference comparator
bits : 0 - 0 (1 bit)
access : read-write

ADCREFKEEPTRIM : ADC Reference Keeper Trim
bits : 8 - 20 (13 bit)
access : read-write

ADCRFCMPEN : ADC Reference comparator power down
bits : 16 - 32 (17 bit)
access : read-write

XTALSWE : XTAL Software Override Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDBKDSBLXTAL : XTAL Oscillator Disable Feedback.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYPCMPRXTAL : XTAL Oscillator Bypass Comparator.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDNBCOREXTAL : XTAL Oscillator Power Down Core.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDNBCMPRXTAL : XTAL Oscillator Power Down Comparator.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWDBODXTAL : XTAL Power down on brown out.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTALIBUFTRIM : XTAL IBUFF trim
bits : 6 - 13 (8 bit)
access : read-write

XTALICOMPTRIM : XTAL ICOMP trim
bits : 8 - 17 (10 bit)
access : read-write

ACWARMUP : Auto-calibration delay control
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTALBIASTRIM : XTAL BIAS trim
bits : 2 - 9 (8 bit)
access : read-write

XTALKSBIASTRIM : XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock.
bits : 8 - 21 (14 bit)
access : read-write

ALLOWBURST : Allow Burst feature
bits : 0 - 0 (1 bit)
access : read-write

ALLOWBLE : Allow BLE feature
bits : 1 - 2 (2 bit)
access : read-write

SECBOOT : Secure boot feature allowed
bits : 2 - 4 (3 bit)
access : read-write

BLEREQ : Controls the BLE functionality
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLEACK : ACK for BLEREQ
bits : 1 - 2 (2 bit)
access : read-write

BLEAVAIL : AVAILABILITY of the BLE functionality
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSTREQ : Controls the Burst functionality
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSTACK : ACK for BURSTREQ
bits : 5 - 10 (6 bit)
access : read-write

BURSTAVAIL : Availability of Burst functionality
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED_RW_0 : Reserved bits, always leave unchanged. The MISCCTRL register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.
bits : 0 - 4 (5 bit)
access : read-write

BLE_RESETN : BLE reset signal.
bits : 5 - 10 (6 bit)
access : read-write

BOOTLOADERLOW : Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBLOCK : Secure boot lock. Always resets to 1, write 1 to clear. Enables system visibility to bootloader until set.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PROTLOCK : Flash protection lock. Always resets to 1, write 1 to clear. Enables writes to flash protection register set.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SECBOOTFEATURE : Indicates whether the secure boot feature is enabled.
bits : 26 - 53 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SECBOOT : Indicates whether the secure boot on cold reset is enabled
bits : 28 - 57 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SECBOOTONRST : Indicates whether the secure boot on warm reset is enabled
bits : 30 - 61 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VALID : Indicates whether the shadow registers contain valid data from the Flash Information Space.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLDSLEEP : Indicates whether the bootloader should sleep or deep sleep if no image loaded.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INFO0_VALID : Indicates whether INFO0 contains valid data
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCRATCH0 : Scratch register 0.
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH1 : Scratch register 1.
bits : 0 - 31 (32 bit)
access : read-write

ICODEFAULTADDR : The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write

DCODEFAULTADDR : The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write

SYSFAULTADDR : SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.
bits : 0 - 31 (32 bit)
access : read-write

ICODEFAULT : The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCODEFAULT : DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSFAULT : SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FAULTCAPTUREEN : Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOCKOUT : Lockout of debugger (SWD).
bits : 0 - 0 (1 bit)
access : read-write

ONETO8 : Read-only register for communication validation
bits : 0 - 31 (32 bit)
access : read-write

COOLCODE : Read-only register for communication validation
bits : 0 - 31 (32 bit)
access : read-write

ENABLE : PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENABLE : TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSEL : This field selects the frequency of the ARM M4 TPIU port.
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTAVALID : Indicates that an OTA update is valid
bits : 0 - 0 (1 bit)
access : read-write

OTASBLUPDATE : Indicates that the sbl_init has been updated
bits : 1 - 2 (2 bit)
access : read-write

OTAPOINTER : Flash page pointer with updated OTA image
bits : 2 - 33 (32 bit)
access : read-write

IPREFETCH : When set, instruction accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Generally, this mode bit should be set for improved performance when executing instructions from SRAM.
bits : 0 - 0 (1 bit)
access : read-write

IPREFETCH_CACHE : Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires IPREFETCH to be set).
bits : 1 - 2 (2 bit)
access : read-write

DPREFETCH : When set, data bus accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses.
bits : 4 - 8 (5 bit)
access : read-write

DPREFETCH_CACHE : Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires DPREFETCH to be set).
bits : 5 - 10 (6 bit)
access : read-write

KEXTCLKSEL : Key register value.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESERVED_RW_0 : Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.
bits : 0 - 15 (16 bit)
access : read-write

SIMOBUCKCORELPHIGHTONTRIM : simobuck_core_lp_high_ton_trim
bits : 16 - 35 (20 bit)
access : read-write

SIMOBUCKCORELPLOWTONTRIM : simobuck_core_lp_low_ton_trim
bits : 20 - 43 (24 bit)
access : read-write

RESERVED_RW_24 : Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.
bits : 24 - 55 (32 bit)
access : read-write

SIMOBUCKCORELPHIGHTOFFTRIM : simobuck_core_lp_high_toff_trim
bits : 0 - 3 (4 bit)
access : read-write

SIMOBUCKCORELPLOWTOFFTRIM : simobuck_core_lp_low_toff_trim
bits : 4 - 11 (8 bit)
access : read-write

SIMOBUCKMEMLPHIGHTOFFTRIM : simobuck_mem_lp_high_toff_trim
bits : 8 - 19 (12 bit)
access : read-write

SIMOBUCKMEMLPLOWTOFFTRIM : simobuck_mem_lp_low_toff_trim
bits : 12 - 27 (16 bit)
access : read-write

RESERVED_RW_16 : Reserved bits, always leave unchanged. The SIMOBUCK3 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.
bits : 16 - 42 (27 bit)
access : read-write

SIMOBUCKMEMLPHIGHTONTRIM : simobuck_mem_lp_high_ton_trim
bits : 27 - 57 (31 bit)
access : read-write

RESERVED_RW_31 : Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.
bits : 31 - 62 (32 bit)
access : read-write

SIMOBUCKMEMLPLOWTONTRIM : simobuck_mem_lp_low_ton_trim
bits : 0 - 3 (4 bit)
access : read-write

SIMOBUCKCLKDIVSEL : simobuck_clkdiv_sel
bits : 21 - 43 (23 bit)
access : read-write

SIMOBUCKCOMP2TIMEOUTEN : simobuck_comp2_timeout_en
bits : 24 - 48 (25 bit)
access : read-write

BLEBUCKTONLOWTRIM : blebuck_ton_low_trim
bits : 0 - 5 (6 bit)
access : read-write

BLEBUCKTONHITRIM : blebuck_ton_hi_trim
bits : 6 - 17 (12 bit)
access : read-write

BLEBUCKTOND2ATRIM : blebuck_ton_trim
bits : 12 - 29 (18 bit)
access : read-write

DMA_WPROT2 : Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.
bits : 0 - 31 (32 bit)
access : read-write

FW0BITS : Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FW1BITS : Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FW2BITS : Write protect flash 0x00100000 - 0x0017FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FW3BITS : Write protect flash 0x00180000 - 0x001FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FR0BITS : Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FR1BITS : Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FR2BITS : Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

FR3BITS : Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)
bits : 0 - 31 (32 bit)
access : read-write

DMA_WPROT0 : Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.
bits : 0 - 31 (32 bit)
access : read-write