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PDM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x294 byte (0x0)
mem_usage : registers
protection :

Registers

PCFG

FIFOFLUSH

FIFOTHR

INTEN

INTSTAT

INTCLR

INTSET

DMATRIGEN

DMATRIGSTAT

DMACFG

DMATOTCOUNT

DMATARGADDR

DMASTAT

VCFG

VOICESTAT

FIFOREAD


PCFG

PDM Configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG PCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMCOREEN SOFTMUTE CYCLES HPCUTOFF ADCHPD SINCRATE MCLKDIV PGALEFT PGARIGHT LRSWAP

PDMCOREEN : Data Streaming Control.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : EN

Enable Data Streaming.

0 : DIS

Disable Data Streaming.

End of enumeration elements list.

SOFTMUTE : Soft mute control.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : EN

Enable Soft Mute.

0 : DIS

Disable Soft Mute.

End of enumeration elements list.

CYCLES : Number of clocks during gain-setting changes.
bits : 2 - 6 (5 bit)
access : read-write

HPCUTOFF : High pass filter coefficients.
bits : 5 - 13 (9 bit)
access : read-write

ADCHPD : High pass filter control.
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : EN

Enable high pass filter.

1 : DIS

Disable high pass filter.

End of enumeration elements list.

SINCRATE : SINC decimation rate.
bits : 10 - 26 (17 bit)
access : read-write

MCLKDIV : PDM_CLK frequency divisor.
bits : 17 - 35 (19 bit)
access : read-write

Enumeration:

3 : MCKDIV4

Divide input clock by 4

2 : MCKDIV3

Divide input clock by 3

1 : MCKDIV2

Divide input clock by 2

0 : MCKDIV1

Divide input clock by 1

End of enumeration elements list.

PGALEFT : Left channel PGA gain.
bits : 21 - 46 (26 bit)
access : read-write

Enumeration:

31 : P405DB

40.5 db gain.

30 : P390DB

39.0 db gain.

29 : P375DB

37.5 db gain.

28 : P360DB

36.0 db gain.

27 : P345DB

34.5 db gain.

26 : P330DB

33.0 db gain.

25 : P315DB

31.5 db gain.

24 : P300DB

30.0 db gain.

23 : P285DB

28.5 db gain.

22 : P270DB

27.0 db gain.

21 : P255DB

25.5 db gain.

20 : P240DB

24.0 db gain.

19 : P225DB

22.5 db gain.

18 : P210DB

21.0 db gain.

17 : P195DB

19.5 db gain.

16 : P180DB

18.0 db gain.

15 : P165DB

16.5 db gain.

14 : P150DB

15.0 db gain.

13 : P135DB

13.5 db gain.

12 : P120DB

12.0 db gain.

11 : P105DB

10.5 db gain.

10 : P90DB

9.0 db gain.

9 : P75DB

7.5 db gain.

8 : P60DB

6.0 db gain.

7 : P45DB

4.5 db gain.

6 : P30DB

3.0 db gain.

5 : P15DB

1.5 db gain.

4 : 0DB

0.0 db gain.

3 : M15DB

-1.5 db gain.

2 : M300DB

-3.0 db gain.

1 : M45DB

-4.5 db gain.

0 : M60DB

-6.0 db gain.

End of enumeration elements list.

PGARIGHT : Right channel PGA gain.
bits : 26 - 56 (31 bit)
access : read-write

Enumeration:

31 : P405DB

40.5 db gain.

30 : P390DB

39.0 db gain.

29 : P375DB

37.5 db gain.

28 : P360DB

36.0 db gain.

27 : P345DB

34.5 db gain.

26 : P330DB

33.0 db gain.

25 : P315DB

31.5 db gain.

24 : P300DB

30.0 db gain.

23 : P285DB

28.5 db gain.

22 : P270DB

27.0 db gain.

21 : P255DB

25.5 db gain.

20 : P240DB

24.0 db gain.

19 : P225DB

22.5 db gain.

18 : P210DB

21.0 db gain.

17 : P195DB

19.5 db gain.

16 : P180DB

18.0 db gain.

15 : P165DB

16.5 db gain.

14 : P150DB

15.0 db gain.

13 : P135DB

13.5 db gain.

12 : P120DB

12.0 db gain.

11 : P105DB

10.5 db gain.

10 : P90DB

9.0 db gain.

9 : P75DB

7.5 db gain.

8 : P60DB

6.0 db gain.

7 : P45DB

4.5 db gain.

6 : P30DB

3.0 db gain.

5 : P15DB

1.5 db gain.

4 : 0DB

0.0 db gain.

3 : M15DB

-1.5 db gain.

2 : M300DB

-3.0 db gain.

1 : M45DB

-4.5 db gain.

0 : M60DB

-6.0 db gain.

End of enumeration elements list.

LRSWAP : Left/right channel swap.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

1 : EN

Swap left and right channels (FIFO Read RIGHT_LEFT).

0 : NOSWAP

No channel swapping (IFO Read LEFT_RIGHT).

End of enumeration elements list.


FIFOFLUSH

FIFO Flush
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOFLUSH FIFOFLUSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOFLUSH

FIFOFLUSH : FIFO FLUSH.
bits : 0 - 0 (1 bit)
access : read-write


FIFOTHR

FIFO Threshold
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOTHR FIFOTHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOTHR

FIFOTHR : FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled)
bits : 0 - 4 (5 bit)
access : read-write


INTEN

IO Master Interrupts: Enable
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR OVF UNDFL DCMP DERR

THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write

OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

DCMP : DMA completed a transfer
bits : 3 - 6 (4 bit)
access : read-write

DERR : DMA Error received
bits : 4 - 8 (5 bit)
access : read-write


INTSTAT

IO Master Interrupts: Status
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR OVF UNDFL DCMP DERR

THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write

OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

DCMP : DMA completed a transfer
bits : 3 - 6 (4 bit)
access : read-write

DERR : DMA Error received
bits : 4 - 8 (5 bit)
access : read-write


INTCLR

IO Master Interrupts: Clear
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR OVF UNDFL DCMP DERR

THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write

OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

DCMP : DMA completed a transfer
bits : 3 - 6 (4 bit)
access : read-write

DERR : DMA Error received
bits : 4 - 8 (5 bit)
access : read-write


INTSET

IO Master Interrupts: Set
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSET INTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR OVF UNDFL DCMP DERR

THR : This is the FIFO threshold interrupt.
bits : 0 - 0 (1 bit)
access : read-write

OVF : This is the FIFO overflow interrupt.
bits : 1 - 2 (2 bit)
access : read-write

UNDFL : This is the FIFO underflow interrupt.
bits : 2 - 4 (3 bit)
access : read-write

DCMP : DMA completed a transfer
bits : 3 - 6 (4 bit)
access : read-write

DERR : DMA Error received
bits : 4 - 8 (5 bit)
access : read-write


DMATRIGEN

DMA Trigger Enable
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATRIGEN DMATRIGEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHR DTHR90

DTHR : Trigger DMA upon when FIFO is filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only
bits : 0 - 0 (1 bit)
access : read-write

DTHR90 : Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function
bits : 1 - 2 (2 bit)
access : read-write


DMATRIGSTAT

DMA Trigger Status
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATRIGSTAT DMATRIGSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTHRSTAT DTHR90STAT

DTHRSTAT : Triggered DMA from FIFO reaching threshold
bits : 0 - 0 (1 bit)
access : read-write

DTHR90STAT : Triggered DMA from FIFO reaching 90 percent full
bits : 1 - 2 (2 bit)
access : read-write


DMACFG

DMA Configuration
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFG DMACFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMADIR DMAPRI DAUTOHIP DPWROFF

DMAEN : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DIS

Disable DMA Function

1 : EN

Enable DMA Function

End of enumeration elements list.

DMADIR : Direction
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : P2M

Peripheral to Memory (SRAM) transaction. THe PDM module will only DMA to memory.

1 : M2P

Memory to Peripheral transaction. Not available for PDM module

End of enumeration elements list.

DMAPRI : Sets the Priority of the DMA request
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : LOW

Low Priority (service as best effort)

1 : HIGH

High Priority (service immediately)

End of enumeration elements list.

DAUTOHIP : Raise priority to high on FIFO full, and DMAPRI set to low
bits : 9 - 18 (10 bit)
access : read-write

DPWROFF : Power Off the ADC System upon DMACPL.
bits : 10 - 20 (11 bit)
access : read-write


DMATOTCOUNT

DMA Total Transfer Count
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATOTCOUNT DMATOTCOUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTCOUNT

TOTCOUNT : Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns.
bits : 0 - 19 (20 bit)
access : read-write


DMATARGADDR

DMA Target Address
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATARGADDR DMATARGADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTARGADDR UTARGADDR

LTARGADDR : DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer.
bits : 0 - 20 (21 bit)
access : read-write

UTARGADDR : SRAM Target
bits : 21 - 52 (32 bit)
access : read-write


DMASTAT

DMA Status
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASTAT DMASTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATIP DMACPL DMAERR

DMATIP : DMA Transfer In Progress
bits : 0 - 0 (1 bit)
access : read-write

DMACPL : DMA Transfer Complete
bits : 1 - 2 (2 bit)
access : read-write

DMAERR : DMA Error
bits : 2 - 4 (3 bit)
access : read-write


VCFG

Voice Configuration
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCFG VCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSET PCMPACK SELAP DMICKDEL BCLKINV I2SEN PDMCLKEN PDMCLKSEL RSTB IOCLKEN

CHSET : Set PCM channels.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : DIS

Channel disabled.

1 : LEFT

Mono left channel.

2 : RIGHT

Mono right channel.

3 : STEREO

Stereo channels.

End of enumeration elements list.

PCMPACK : PCM data packing enable.
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : DIS

Disable PCM packing.

1 : EN

Enable PCM packing.

End of enumeration elements list.

SELAP : Select PDM input clock source.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

1 : I2S

Clock source from I2S BCLK.

0 : INTERNAL

Clock source from internal clock generator.

End of enumeration elements list.

DMICKDEL : PDM clock sampling delay.
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : 0CYC

No delay.

1 : 1CYC

1 cycle delay.

End of enumeration elements list.

BCLKINV : I2S BCLK input inversion.
bits : 19 - 38 (20 bit)
access : read-write

Enumeration:

0 : INV

BCLK inverted.

1 : NORM

BCLK not inverted.

End of enumeration elements list.

I2SEN : I2S interface enable.
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

0 : DIS

Disable I2S interface.

1 : EN

Enable I2S interface.

End of enumeration elements list.

PDMCLKEN : Enable the serial clock.
bits : 26 - 52 (27 bit)
access : read-write

Enumeration:

0 : DIS

Disable serial clock.

1 : EN

Enable serial clock.

End of enumeration elements list.

PDMCLKSEL : Select the PDM input clock.
bits : 27 - 56 (30 bit)
access : read-write

Enumeration:

0 : DISABLE

Static value.

1 : 12MHz

PDM clock is 12 MHz.

2 : 6MHz

PDM clock is 6 MHz.

3 : 3MHz

PDM clock is 3 MHz.

4 : 1_5MHz

PDM clock is 1.5 MHz.

5 : 750KHz

PDM clock is 750 KHz.

6 : 375KHz

PDM clock is 375 KHz.

7 : 187KHz

PDM clock is 187.5 KHz.

End of enumeration elements list.

RSTB : Reset the IP core.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

0 : RESET

Reset the core.

1 : NORM

Enable the core.

End of enumeration elements list.

IOCLKEN : Enable the IO clock.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

0 : DIS

Disable FIFO read.

1 : EN

Enable FIFO read.

End of enumeration elements list.


VOICESTAT

Voice Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VOICESTAT VOICESTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOCNT

FIFOCNT : Valid 32-bit entries currently in the FIFO.
bits : 0 - 5 (6 bit)
access : read-write


FIFOREAD

FIFO Read
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOREAD FIFOREAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOREAD

FIFOREAD : FIFO read data.
bits : 0 - 31 (32 bit)
access : read-write



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