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PWRCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

SUPPLYSRC

MEMPWREN

MEMPWRSTATUS

DEVPWRSTATUS

SRAMCTRL

ADCSTATUS

MISC

DEVPWREVENTEN

MEMPWREVENTEN

SUPPLYSTATUS

DEVPWREN

MEMPWDINSLEEP


SUPPLYSRC

Voltage Regulator Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUPPLYSRC SUPPLYSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEBUCKEN

BLEBUCKEN : Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : EN

Enable the BLE Buck.

0 : DIS

Disable the BLE Buck.

End of enumeration elements list.


MEMPWREN

Enables individual banks of the MEMORY array
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPWREN MEMPWREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCM SRAM FLASH0 FLASH1 CACHEB0 CACHEB2

DTCM : Power up DTCM
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE

Do not enable power to any DTCMs

1 : GROUP0DTCM0

Power ON only 8KB GROUP0_DTCM0 (0 - 8KB, addr: 0x10000000 - 0x10001FFF)

2 : GROUP0DTCM1

Power ON only 24KB GROUP0_DTCM1 (8KB - 32KB, addr: 0x10002000 - 0x10007FFF)

3 : GROUP0

Power ON only DTCMs in 32KB group0 (0 - 32KB, addr: 0x10000000 - 0x10007FFF)

4 : GROUP1

Power ON only DTCMs in 32KB group1 (32KB - 64KB, addr: 0x10008000 - 0x1000FFFF)

7 : ALL

Power ON all DTCMs (0 - 64KB, addr: 0x10000000 - 0x1000FFFF)

End of enumeration elements list.

SRAM : Power up SRAM groups
bits : 3 - 15 (13 bit)
access : read-write

Enumeration:

0 : NONE

Do not power ON any of the SRAM banks

1 : GROUP0

Power ON only SRAM 64KB group0 (addr: 0x10010000 - 0x1001FFFF)

2 : GROUP1

Power ON only SRAM 64KB group1 (addr: 0x10020000 - 0x1002FFFF)

4 : GROUP2

Power ON only SRAM 64KB group2 (addr: 0x10030000 - 0x1003FFFF)

8 : GROUP3

Power ON only SRAM 64KB group3 (addr: 0x10040000 - 0x1004FFFF)

16 : GROUP4

Power ON only SRAM 64KB group4 (addr: 0x10050000 - 0x1005FFFF)

32 : GROUP5

Power ON only SRAM 64KB group5 (addr: 0x10060000 - 0x1006FFFF)

64 : GROUP6

Power ON only SRAM 64KB group6 (addr: 0x10070000 - 0x1007FFFF)

128 : GROUP7

Power ON only SRAM 64KB group7 (addr: 0x10080000 - 0x1008FFFF)

256 : GROUP8

Power ON only SRAM 96KB group8 (addr: 0x10090000 - 0x100A7FFF)

512 : GROUP9

Power ON only SRAM 96KB group9 (addr: 0x100A8000 - 0x100BFFFF)

3 : SRAM128K

Power ON only lower 128k (addr: 0x10010000 - 0x1002FFFF)

15 : SRAM256K

Power ON only lower 256k (addr: 0x10010000 - 0x1004FFFF)

255 : SRAM512K

Power ON only lower 512k (addr: 0x10010000 - 0x1008FFFF)

1023 : ALL

All SRAM banks (704K) powered ON (addr: 0x10010000 - 0x100BFFFF)

End of enumeration elements list.

FLASH0 : Power up FLASH group 0 (0MB-1MB)
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : EN

Power up FLASH group 0 (0MB-1MB)

0 : DIS

Power down FLASH group 0 (0MB-1MB)

End of enumeration elements list.

FLASH1 : Power up FLASH group 1 (1MB-2MB)
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : EN

Power up FLASH group 1 (1MB-2MB)

0 : DIS

Power down FLASH group 1 (1MB-2MB)

End of enumeration elements list.

CACHEB0 : Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 0, cache has to be enabled and this bit has to be set.
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : EN

Power up Cache Bank 0

0 : DIS

Power down Cache Bank 0

End of enumeration elements list.

CACHEB2 : Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 2, cache has to be enabled and this bit has to be set.
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

1 : EN

Power up Cache Bank 2

0 : DIS

Power down Cache Bank 2

End of enumeration elements list.


MEMPWRSTATUS

Mem Power ON Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPWRSTATUS MEMPWRSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCM00 DTCM01 DTCM1 SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 FLASH0 FLASH1 CACHEB0 CACHEB2

DTCM00 : This bit is 1 if power is supplied to DTCM GROUP0_0
bits : 0 - 0 (1 bit)
access : read-write

DTCM01 : This bit is 1 if power is supplied to DTCM GROUP0_1
bits : 1 - 2 (2 bit)
access : read-write

DTCM1 : This bit is 1 if power is supplied to DTCM GROUP1
bits : 2 - 4 (3 bit)
access : read-write

SRAM0 : This bit is 1 if power is supplied to SRAM GROUP0
bits : 3 - 6 (4 bit)
access : read-write

SRAM1 : This bit is 1 if power is supplied to SRAM GROUP1
bits : 4 - 8 (5 bit)
access : read-write

SRAM2 : This bit is 1 if power is supplied to SRAM GROUP2
bits : 5 - 10 (6 bit)
access : read-write

SRAM3 : This bit is 1 if power is supplied to SRAM GROUP3
bits : 6 - 12 (7 bit)
access : read-write

SRAM4 : This bit is 1 if power is supplied to SRAM GROUP4
bits : 7 - 14 (8 bit)
access : read-write

SRAM5 : This bit is 1 if power is supplied to SRAM GROUP5
bits : 8 - 16 (9 bit)
access : read-write

SRAM6 : This bit is 1 if power is supplied to SRAM GROUP6
bits : 9 - 18 (10 bit)
access : read-write

SRAM7 : This bit is 1 if power is supplied to SRAM GROUP7
bits : 10 - 20 (11 bit)
access : read-write

SRAM8 : This bit is 1 if power is supplied to SRAM GROUP8
bits : 11 - 22 (12 bit)
access : read-write

SRAM9 : This bit is 1 if power is supplied to SRAM GROUP9
bits : 12 - 24 (13 bit)
access : read-write

FLASH0 : This bit is 1 if power is supplied to FLASH group 0
bits : 13 - 26 (14 bit)
access : read-write

FLASH1 : This bit is 1 if power is supplied to FLASH group 1
bits : 14 - 28 (15 bit)
access : read-write

CACHEB0 : This bit is 1 if power is supplied to Cache Bank 0
bits : 15 - 30 (16 bit)
access : read-write

CACHEB2 : This bit is 1 if power is supplied to Cache Bank 2
bits : 16 - 32 (17 bit)
access : read-write


DEVPWRSTATUS

Device Power ON Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVPWRSTATUS DEVPWRSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCUL MCUH HCPA HCPB HCPC PWRADC PWRMSPI PWRPDM BLEL BLEH

MCUL : This bit is 1 if power is supplied to MCUL
bits : 0 - 0 (1 bit)
access : read-write

MCUH : This bit is 1 if power is supplied to MCUH
bits : 1 - 2 (2 bit)
access : read-write

HCPA : This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD)
bits : 2 - 4 (3 bit)
access : read-write

HCPB : This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2)
bits : 3 - 6 (4 bit)
access : read-write

HCPC : This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6)
bits : 4 - 8 (5 bit)
access : read-write

PWRADC : This bit is 1 if power is supplied to ADC
bits : 5 - 10 (6 bit)
access : read-write

PWRMSPI : This bit is 1 if power is supplied to MSPI
bits : 6 - 12 (7 bit)
access : read-write

PWRPDM : This bit is 1 if power is supplied to PDM
bits : 7 - 14 (8 bit)
access : read-write

BLEL : This bit is 1 if power is supplied to BLEL
bits : 8 - 16 (9 bit)
access : read-write

BLEH : This bit is 1 if power is supplied to BLEH
bits : 9 - 18 (10 bit)
access : read-write


SRAMCTRL

SRAM Control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAMCTRL SRAMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAMCLKGATE SRAMMASTERCLKGATE SRAMLIGHTSLEEP

SRAMCLKGATE : This bit is 1 if clock gating is allowed for individual system SRAMs
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : EN

Enable Individual SRAM Clock Gating

0 : DIS

Disables Individual SRAM Clock Gating

End of enumeration elements list.

SRAMMASTERCLKGATE : This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block)
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : EN

Enable Master SRAM Clock Gate

0 : DIS

Disables Master SRAM Clock Gating

End of enumeration elements list.

SRAMLIGHTSLEEP : Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses.
bits : 8 - 27 (20 bit)
access : read-write

Enumeration:

255 : ALL

Enable LIGHT SLEEP for ALL SRAMs

0 : DIS

Disables LIGHT SLEEP for ALL SRAMs

End of enumeration elements list.


ADCSTATUS

Power Status Register for ADC Block
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCSTATUS ADCSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCPWD BGTPWD VPTATPWD VBATPWD REFKEEPPWD REFBUFPWD

ADCPWD : This bit indicates that the ADC is powered down
bits : 0 - 0 (1 bit)
access : read-write

BGTPWD : This bit indicates that the ADC Band Gap is powered down
bits : 1 - 2 (2 bit)
access : read-write

VPTATPWD : This bit indicates that the ADC temperature sensor input buffer is powered down
bits : 2 - 4 (3 bit)
access : read-write

VBATPWD : This bit indicates that the ADC VBAT resistor divider is powered down
bits : 3 - 6 (4 bit)
access : read-write

REFKEEPPWD : This bit indicates that the ADC REFKEEP is powered down
bits : 4 - 8 (5 bit)
access : read-write

REFBUFPWD : This bit indicates that the ADC REFBUF is powered down
bits : 5 - 10 (6 bit)
access : read-write


MISC

Power Optimization Control Bits
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC MISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCEMEMVRLPTIMERS MEMVRLPBLE

FORCEMEMVRLPTIMERS : Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running.
bits : 3 - 6 (4 bit)
access : read-write

MEMVRLPBLE : Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : EN

Mem VR can go to lp mode even when BLE is powered on.

0 : DIS

Mem VR will stay in active mode when BLE is powered on.

End of enumeration elements list.


DEVPWREVENTEN

Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVPWREVENTEN DEVPWREVENTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCULEVEN MCUHEVEN HCPAEVEN HCPBEVEN HCPCEVEN ADCEVEN MSPIEVEN PDMEVEN BLELEVEN BLEFEATUREEVEN BURSTFEATUREEVEN BURSTEVEN

MCULEVEN : Control MCUL power-on status event
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : EN

Enable MCUL power-on status event

0 : DIS

Disable MCUL power-on status event

End of enumeration elements list.

MCUHEVEN : Control MCUH power-on status event
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : EN

Enable MCHU power-on status event

0 : DIS

Disable MCUH power-on status event

End of enumeration elements list.

HCPAEVEN : Control HCPA power-on status event
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : EN

Enable HCPA power-on status event

0 : DIS

Disable HCPA power-on status event

End of enumeration elements list.

HCPBEVEN : Control HCPB power-on status event
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : EN

Enable HCPB power-on status event

0 : DIS

Disable HCPB power-on status event

End of enumeration elements list.

HCPCEVEN : Control HCPC power-on status event
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : EN

Enable HCPC power-on status event

0 : DIS

Disable HCPC power-on status event

End of enumeration elements list.

ADCEVEN : Control ADC power-on status event
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : EN

Enable ADC power-on status event

0 : DIS

Disable ADC power-on status event

End of enumeration elements list.

MSPIEVEN : Control MSPI power-on status event
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : EN

Enable MSPI power-on status event

0 : DIS

Disable MSPI power-on status event

End of enumeration elements list.

PDMEVEN : Control PDM power-on status event
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : EN

Enable PDM power-on status event

0 : DIS

Disable PDM power-on status event

End of enumeration elements list.

BLELEVEN : Control BLE power-on status event
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : EN

Enable BLE power-on status event

0 : DIS

Disable BLE power-on status event

End of enumeration elements list.

BLEFEATUREEVEN : Control BLEFEATURE status event
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

1 : EN

Enable BLEFEATURE status event

0 : DIS

Disable BLEFEATURE status event

End of enumeration elements list.

BURSTFEATUREEVEN : Control BURSTFEATURE status event
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : EN

Enable BURSTFEATURE status event

0 : DIS

Disable BURSTFEATURE status event

End of enumeration elements list.

BURSTEVEN : Control BURST status event
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

1 : EN

Enable BURST status event

0 : DIS

Disable BURST status event

End of enumeration elements list.


MEMPWREVENTEN

Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPWREVENTEN MEMPWREVENTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCMEN SRAMEN FLASH0EN FLASH1EN CACHEB0EN CACHEB2EN

DTCMEN : Enable DTCM power-on status event
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE

Do not enable DTCM power-on status event

1 : GROUP0DTCM0EN

Enable GROUP0_DTCM0 power on status event

2 : GROUP0DTCM1EN

Enable GROUP0_DTCM1 power on status event

3 : GROUP0EN

Enable DTCMs in group0 power on status event

4 : GROUP1EN

Enable DTCMs in group1 power on status event

7 : ALL

Enable all DTCM power on status event

End of enumeration elements list.

SRAMEN : Control SRAM power-on status event
bits : 3 - 15 (13 bit)
access : read-write

Enumeration:

0 : NONE

Disable SRAM power-on status event

1 : GROUP0EN

Enable SRAM group0 (0KB-32KB) power on status event

2 : GROUP1EN

Enable SRAM group1 (32KB-64KB) power on status event

4 : GROUP2EN

Enable SRAM group2 (64KB-96KB) power on status event

8 : GROUP3EN

Enable SRAM group3 (96KB-128KB) power on status event

16 : GROUP4EN

Enable SRAM group4 (128KB-160KB) power on status event

32 : GROUP5EN

Enable SRAM group5 (160KB-192KB) power on status event

64 : GROUP6EN

Enable SRAM group6 (192KB-224KB) power on status event

128 : GROUP7EN

Enable SRAM group7 (224KB-256KB) power on status event

256 : GROUP8EN

Enable SRAM group8 (256KB-288KB) power on status event

512 : GROUP9EN

Enable SRAM group9 (288KB-320KB) power on status event

End of enumeration elements list.

FLASH0EN : Control FLASH power-on status event
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : EN

Enable FLASH status event

0 : DIS

Disables FLASH status event

End of enumeration elements list.

FLASH1EN : Control FLASH power-on status event
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : EN

Enable FLASH status event

0 : DIS

Disables FLASH status event

End of enumeration elements list.

CACHEB0EN : Control CACHE BANK 0 power-on status event
bits : 30 - 60 (31 bit)
access : read-write

Enumeration:

1 : EN

Enable CACHE BANK 0 status event

0 : DIS

Disable CACHE BANK 0 status event

End of enumeration elements list.

CACHEB2EN : Control CACHEB2 power-on status event
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

1 : EN

Enable CACHE BANK 2 status event

0 : DIS

Disable CACHE BANK 2 status event

End of enumeration elements list.


SUPPLYSTATUS

Voltage Regulators status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUPPLYSTATUS SUPPLYSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIMOBUCKON BLEBUCKON

SIMOBUCKON : Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : OFF

Indicates the the SIMO Buck is OFF.

1 : ON

Indicates the the SIMO Buck is ON.

End of enumeration elements list.

BLEBUCKON : Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : LDO

Indicates the the LDO is supplying the BLE/Burst power domain

1 : BUCK

Indicates the the Buck is supplying the BLE/Burst power domain

End of enumeration elements list.


DEVPWREN

Device Power Enables
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVPWREN DEVPWREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRIOS PWRIOM0 PWRIOM1 PWRIOM2 PWRIOM3 PWRIOM4 PWRIOM5 PWRUART0 PWRUART1 PWRADC PWRSCARD PWRMSPI0 PWRMSPI1 PWRMSPI2 PWRPDM PWRBLEL

PWRIOS : Power up IO Slave
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : EN

Power up IO slave

0 : DIS

Power down IO slave

End of enumeration elements list.

PWRIOM0 : Power up IO Master 0
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 0

0 : DIS

Power down IO Master 0

End of enumeration elements list.

PWRIOM1 : Power up IO Master 1
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 1

0 : DIS

Power down IO Master 1

End of enumeration elements list.

PWRIOM2 : Power up IO Master 2
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 2

0 : DIS

Power down IO Master 2

End of enumeration elements list.

PWRIOM3 : Power up IO Master 3
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 3

0 : DIS

Power down IO Master 3

End of enumeration elements list.

PWRIOM4 : Power up IO Master 4
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 4

0 : DIS

Power down IO Master 4

End of enumeration elements list.

PWRIOM5 : Power up IO Master 5
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : EN

Power up IO Master 5

0 : DIS

Power down IO Master 5

End of enumeration elements list.

PWRUART0 : Power up UART Controller 0
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

1 : EN

Power up UART 0

0 : DIS

Power down UART 0

End of enumeration elements list.

PWRUART1 : Power up UART Controller 1
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

1 : EN

Power up UART 1

0 : DIS

Power down UART 1

End of enumeration elements list.

PWRADC : Power up ADC Digital Controller
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

1 : EN

Power up ADC

0 : DIS

Power Down ADC

End of enumeration elements list.

PWRSCARD : Power up SCARD Controller
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

1 : EN

Power up SCARD

0 : DIS

Power down SCARD

End of enumeration elements list.

PWRMSPI0 : Power up MSPI0 Controller
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

1 : EN

Power up MSPI0

0 : DIS

Power down MSPI0

End of enumeration elements list.

PWRMSPI1 : Power up MSPI1 Controller
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

1 : EN

Power up MSPI1

0 : DIS

Power down MSPI1

End of enumeration elements list.

PWRMSPI2 : Power up MSPI2 Controller
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : EN

Power up MSPI2

0 : DIS

Power down MSPI2

End of enumeration elements list.

PWRPDM : Power up PDM block
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : EN

Power up PDM

0 : DIS

Power down PDM

End of enumeration elements list.

PWRBLEL : Power up BLE controller
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

1 : EN

Power up BLE controller

0 : DIS

Power down BLE controller

End of enumeration elements list.


MEMPWDINSLEEP

Power-down SRAM banks in Deep Sleep mode
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPWDINSLEEP MEMPWDINSLEEP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCMPWDSLP SRAMPWDSLP FLASH0PWDSLP FLASH1PWDSLP CACHEPWDSLP

DTCMPWDSLP : power down DTCM in deep sleep
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE

All DTCM retained

1 : GROUP0DTCM0

Group0_DTCM0 powered down in deep sleep (0KB-8KB)

2 : GROUP0DTCM1

Group0_DTCM1 powered down in deep sleep (8KB-32KB)

3 : GROUP0

Both DTCMs in group0 are powered down in deep sleep (0KB-32KB)

6 : ALLBUTGROUP0DTCM0

Group1 and Group0_DTCM1 are powered down in deep sleep (8KB-64KB)

4 : GROUP1

Group1 DTCM powered down in deep sleep (32KB-64KB)

7 : ALL

All DTCMs powered down in deep sleep (0KB-64KB)

End of enumeration elements list.

SRAMPWDSLP : Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.
bits : 3 - 15 (13 bit)
access : read-write

Enumeration:

0 : NONE

All banks retained

1 : GROUP0

SRAM GROUP0 powered down (64KB-128KB)

2 : GROUP1

SRAM GROUP1 powered down (128KB-192KB)

4 : GROUP2

SRAM GROUP2 powered down (192KB-256KB)

8 : GROUP3

SRAM GROUP3 powered down (256KB-320KB)

16 : GROUP4

SRAM GROUP4 powered down (320KB-384KB)

32 : GROUP5

SRAM GROUP5 powered down (384KB-448KB)

64 : GROUP6

SRAM GROUP6 powered down (448KB-512KB)

128 : GROUP7

SRAM GROUP7 powered down (512KB-576KB)

256 : GROUP8

SRAM GROUP8 powered down (576KB-672KB)

512 : GROUP9

SRAM GROUP9 powered down (672KB-768KB)

3 : SRAM128K

Power-down lower 128k SRAM (64KB-192KB)

15 : SRAM256K

Power-down lower 256k SRAM (64KB-320KB)

1022 : ALLBUTLOWER64K

All SRAM banks but lower 64k powered down.

1020 : ALLBUTLOWER128K

All banks but lower 128k powered down.

1008 : ALLBUTLOWER256K

All banks but lower 256k powered down.

1023 : ALL

All banks powered down.

End of enumeration elements list.

FLASH0PWDSLP : Power-down FLASH0 in deep sleep
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

1 : EN

FLASH0 is powered down during deep sleep

0 : DIS

FLASH0 is kept powered on during deep sleep

End of enumeration elements list.

FLASH1PWDSLP : Power-down FLASH1 in deep sleep
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

1 : EN

FLASH1 is powered down during deep sleep

0 : DIS

FLASH1 is kept powered on during deep sleep

End of enumeration elements list.

CACHEPWDSLP : power down cache in deep sleep
bits : 31 - 62 (32 bit)
access : read-write

Enumeration:

1 : EN

Power down cache in deep sleep

0 : DIS

Retain cache in deep sleep

End of enumeration elements list.



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