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SCARD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x104 byte (0x0)
mem_usage : registers
protection :

Registers

SR

DR

CLKCTRL

BPRL

BPRH

UCR1

SR1

IER1

ECNTL

ECNTH

GTR

RETXCNT

RETXCNTRMI

IER

TCR

UCR


SR

ISO7816 interrupt status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNE TBERBF FER OVR PE FT2REND FHF

FNE : RX FIFO not empty.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : NOTEMPTY

RX FIFO not empty.

0 : EMPTY

RX FIFO empty.

End of enumeration elements list.

TBERBF : FIFO empty (transmit) or full (receive).
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : TXFIFOEMPTY

Transmit: FIFO empty.

0 : TXFIFONOTEMPTY

Transmit: FIFO not empty.

End of enumeration elements list.

FER : Framing error.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : FRAMINGERR

Framing error.

0 : NOFRAMINGERR

No framing error detected.

End of enumeration elements list.

OVR : RX FIFO overflow.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : RXOVR

RX FIFO overflow.

0 : RXOVRNONE

RX FIFO no overflow.

End of enumeration elements list.

PE : Parity Error.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

1 : PEERR

Parity error.

0 : PENONE

No parity error.

End of enumeration elements list.

FT2REND : TX to RX finished.
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

1 : CMPL

TX to RX completed.

0 : NOTCMPL

TX to RX not completed.

End of enumeration elements list.

FHF : FIFO Half Full.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

1 : HALFFULL

FIFO is half full.

End of enumeration elements list.


DR

ISO7816 data
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : Data register.
bits : 0 - 7 (8 bit)
access : read-write


CLKCTRL

Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKEN APBCLKEN

CLKEN : Enable the serial source clock for SCARD.
bits : 0 - 0 (1 bit)
access : read-write

APBCLKEN : Enable the SCARD APB clock to run continuously.
bits : 1 - 2 (2 bit)
access : read-write


BPRL

ISO7816 baud rate low
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPRL BPRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BPRL

BPRL : Baud rate low
bits : 0 - 7 (8 bit)
access : read-write


BPRH

ISO7816 baud rate high
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPRH BPRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BPRH

BPRH : Baud rate high
bits : 0 - 3 (4 bit)
access : read-write


UCR1

ISO7816 user control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCR1 UCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR STSP T1PAREN CLKIOV ENLASTB

PR : Query Card Detect.
bits : 0 - 0 (1 bit)
access : read-write

STSP : ETU counter control. This bit is write-only.
bits : 2 - 4 (3 bit)
access : read-write

T1PAREN : Parity check control.
bits : 3 - 6 (4 bit)
access : read-write

CLKIOV : Output clock level.
bits : 4 - 8 (5 bit)
access : read-write

ENLASTB : Enable last byte function.
bits : 5 - 10 (6 bit)
access : read-write


SR1

ISO7816 interrupt status 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECNTOVER PRL SYNCEND IDLE

ECNTOVER : ETU counter overflow.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

1 : OVR

ETU overflow.

End of enumeration elements list.

PRL : Card insert/remove.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

1 : INSREM

Card inserted/removed.

End of enumeration elements list.

SYNCEND : Write complete synchronization.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

1 : CMPL

Synchronization complete.

0 : INCMPL

Incomplete.

End of enumeration elements list.

IDLE : ISO7816 idle.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

1 : IDLE

ISO7816 idle.

0 : ACTIVE

ISO7816 active.

End of enumeration elements list.


IER1

ISO7816 interrupt enable 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER1 IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECNTOVEREN PRLEN SYNCENDEN

ECNTOVEREN : ETU counter overflow interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write

PRLEN : Card insert/remove interrupt enable.
bits : 1 - 2 (2 bit)
access : read-write

SYNCENDEN : Write complete synchronization interrupt enable.
bits : 2 - 4 (3 bit)
access : read-write


ECNTL

ETU counter low
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECNTL ECNTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECNTL

ECNTL : ETU counter low register.
bits : 0 - 7 (8 bit)
access : read-write


ECNTH

ETU counter high
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECNTH ECNTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECNTH

ECNTH : ETU counter high register.
bits : 0 - 7 (8 bit)
access : read-write


GTR

ISO7816 guard time configuration
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GTR GTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GTR

GTR : Guard time configuration register.
bits : 0 - 7 (8 bit)
access : read-write


RETXCNT

ISO7816 resend count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RETXCNT RETXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RETXCNT

RETXCNT : Resend count register.
bits : 0 - 3 (4 bit)
access : read-write


RETXCNTRMI

ISO7816 resent count inquiry
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RETXCNTRMI RETXCNTRMI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RETXCNTRMI

RETXCNTRMI : Resent count inquiry register.
bits : 0 - 3 (4 bit)
access : read-write


IER

ISO7816 interrupt enable
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNEEN TBERBFEN FEREN OVREN PEEN FT2RENDEN FHFEN

FNEEN : RX FIFO not empty interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write

TBERBFEN : FIFO empty (transmit) or full (receive) interrupt enable.
bits : 1 - 2 (2 bit)
access : read-write

FEREN : Framing error interrupt enable.
bits : 2 - 4 (3 bit)
access : read-write

OVREN : RX FIFOI overflow interrupt enable.
bits : 3 - 6 (4 bit)
access : read-write

PEEN : Parity Error interrupt enable.
bits : 4 - 8 (5 bit)
access : read-write

FT2RENDEN : TX to RX finished interrupt enable.
bits : 5 - 10 (6 bit)
access : read-write

FHFEN : FIFO Half Full interrupt enable.
bits : 6 - 12 (7 bit)
access : read-write


TCR

ISO7816 transmit control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONV SS LCT TR PROT AUTOCONV FIP DMAMD

CONV : Conversion inversion control.
bits : 0 - 0 (1 bit)
access : read-write

SS : Use first byte to configure conversion.
bits : 1 - 2 (2 bit)
access : read-write

LCT : Fast TX to RX.
bits : 2 - 4 (3 bit)
access : read-write

TR : Transmit/receive mode.
bits : 3 - 6 (4 bit)
access : read-write

PROT : PROT control.
bits : 4 - 8 (5 bit)
access : read-write

AUTOCONV : Automatic conversion.
bits : 5 - 10 (6 bit)
access : read-write

FIP : Parity select.
bits : 6 - 12 (7 bit)
access : read-write

DMAMD : DMA direction.
bits : 7 - 14 (8 bit)
access : read-write


UCR

ISO7816 user control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCR UCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CST RIU RSTIN RETXEN

CST : Clock control.
bits : 0 - 0 (1 bit)
access : read-write

RIU : ISO7816 reset. This bit is write-only.
bits : 1 - 2 (2 bit)
access : read-write

RSTIN : Reset polarity.
bits : 2 - 4 (3 bit)
access : read-write

RETXEN : Enable TX/RX time configuration.
bits : 3 - 6 (4 bit)
access : read-write



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