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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x51 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

SR

SMPR2

JOFR1

JOFR2

JOFR3

JOFR4

HTR

LTR

SQR1

SQR2

CSR

CCR

SQR3

JSQR

JDR1

CR1

JDR2

JDR3

JDR4

DR

CR2

SMPR1


SR

status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD EOC JEOC JSTRT STRT OVR

AWD : Analog watchdog flag
bits : 0 - 0 (1 bit)

EOC : Regular channel end of conversion
bits : 1 - 1 (1 bit)

JEOC : Injected channel end of conversion
bits : 2 - 2 (1 bit)

JSTRT : Injected channel start flag
bits : 3 - 3 (1 bit)

STRT : Regular channel start flag
bits : 4 - 4 (1 bit)

OVR : Overrun
bits : 5 - 5 (1 bit)


SMPR2

sample time register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR2 SMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPx_x

SMPx_x : Sample time bits
bits : 0 - 31 (32 bit)


JOFR1

injected channel data offset register x
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR1 JOFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET1

JOFFSET1 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


JOFR2

injected channel data offset register x
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR2 JOFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET2

JOFFSET2 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


JOFR3

injected channel data offset register x
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR3 JOFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET3

JOFFSET3 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


JOFR4

injected channel data offset register x
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JOFR4 JOFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET4

JOFFSET4 : Data offset for injected channel x
bits : 0 - 11 (12 bit)


HTR

watchdog higher threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HTR HTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HT

HT : Analog watchdog higher threshold
bits : 0 - 11 (12 bit)


LTR

watchdog lower threshold register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LTR LTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT

LT : Analog watchdog lower threshold
bits : 0 - 11 (12 bit)


SQR1

regular sequence register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR1 SQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ13 SQ14 SQ15 SQ16 L

SQ13 : 13th conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ14 : 14th conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ15 : 15th conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ16 : 16th conversion in regular sequence
bits : 15 - 19 (5 bit)

L : Regular channel sequence length
bits : 20 - 23 (4 bit)


SQR2

regular sequence register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR2 SQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ7 SQ8 SQ9 SQ10 SQ11 SQ12

SQ7 : 7th conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ8 : 8th conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ9 : 9th conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ10 : 10th conversion in regular sequence
bits : 15 - 19 (5 bit)

SQ11 : 11th conversion in regular sequence
bits : 20 - 24 (5 bit)

SQ12 : 12th conversion in regular sequence
bits : 25 - 29 (5 bit)


CSR

Common status register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD1 EOC1 JEOC1 JSTRT1 STRT1 OVR1

AWD1 : Analog watchdog flag of ADC1
bits : 0 - 0 (1 bit)

EOC1 : End of conversion of ADC1
bits : 1 - 1 (1 bit)

JEOC1 : Injected channel end of conversion of ADC1
bits : 2 - 2 (1 bit)

JSTRT1 : Injected channel Start flag of ADC1
bits : 3 - 3 (1 bit)

STRT1 : Regular channel Start flag of ADC1
bits : 4 - 4 (1 bit)

OVR1 : Overrun flag of ADC1
bits : 5 - 5 (1 bit)


CCR

common control register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCPRE VBATE TSVREFE

ADCPRE : ADC prescaler
bits : 16 - 17 (2 bit)

VBATE : VBAT enable
bits : 22 - 22 (1 bit)

TSVREFE : Temperature sensor and VREFINT enable
bits : 23 - 23 (1 bit)


SQR3

regular sequence register 3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQR3 SQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6

SQ1 : 1st conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ2 : 2nd conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ3 : 3rd conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ4 : 4th conversion in regular sequence
bits : 15 - 19 (5 bit)

SQ5 : 5th conversion in regular sequence
bits : 20 - 24 (5 bit)

SQ6 : 6th conversion in regular sequence
bits : 25 - 29 (5 bit)


JSQR

injected sequence register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JSQR JSQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JSQ1 JSQ2 JSQ3 JSQ4 JL

JSQ1 : 1st conversion in injected sequence
bits : 0 - 4 (5 bit)

JSQ2 : 2nd conversion in injected sequence
bits : 5 - 9 (5 bit)

JSQ3 : 3rd conversion in injected sequence
bits : 10 - 14 (5 bit)

JSQ4 : 4th conversion in injected sequence
bits : 15 - 19 (5 bit)

JL : Injected sequence length
bits : 20 - 21 (2 bit)


JDR1

injected data register x
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR1 JDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : Injected data
bits : 0 - 15 (16 bit)


CR1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDCH EOCIE AWDIE JEOCIE SCAN AWDSGL JAUTO DISCEN JDISCEN DISCNUM JAWDEN AWDEN RES OVRIE

AWDCH : Analog watchdog channel select bits
bits : 0 - 4 (5 bit)

EOCIE : Interrupt enable for EOC
bits : 5 - 5 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 6 - 6 (1 bit)

JEOCIE : Interrupt enable for injected channels
bits : 7 - 7 (1 bit)

SCAN : Scan mode
bits : 8 - 8 (1 bit)

AWDSGL : Enable the watchdog on a single channel in scan mode
bits : 9 - 9 (1 bit)

JAUTO : Automatic injected group conversion
bits : 10 - 10 (1 bit)

DISCEN : Discontinuous mode on regular channels
bits : 11 - 11 (1 bit)

JDISCEN : Discontinuous mode on injected channels
bits : 12 - 12 (1 bit)

DISCNUM : Discontinuous mode channel count
bits : 13 - 15 (3 bit)

JAWDEN : Analog watchdog enable on injected channels
bits : 22 - 22 (1 bit)

AWDEN : Analog watchdog enable on regular channels
bits : 23 - 23 (1 bit)

RES : Resolution
bits : 24 - 25 (2 bit)

OVRIE : Overrun interrupt enable
bits : 26 - 26 (1 bit)


JDR2

injected data register x
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR2 JDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : Injected data
bits : 0 - 15 (16 bit)


JDR3

injected data register x
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR3 JDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : Injected data
bits : 0 - 15 (16 bit)


JDR4

injected data register x
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JDR4 JDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : Injected data
bits : 0 - 15 (16 bit)


DR

regular data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Regular data
bits : 0 - 15 (16 bit)


CR2

control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CONT DMA DDS EOCS ALIGN JEXTSEL JEXTEN JSWSTART EXTSEL EXTEN SWSTART

ADON : A/D Converter ON / OFF
bits : 0 - 0 (1 bit)

CONT : Continuous conversion
bits : 1 - 1 (1 bit)

DMA : Direct memory access mode (for single ADC mode)
bits : 8 - 8 (1 bit)

DDS : DMA disable selection (for single ADC mode)
bits : 9 - 9 (1 bit)

EOCS : End of conversion selection
bits : 10 - 10 (1 bit)

ALIGN : Data alignment
bits : 11 - 11 (1 bit)

JEXTSEL : External event select for injected group
bits : 16 - 19 (4 bit)

JEXTEN : External trigger enable for injected channels
bits : 20 - 21 (2 bit)

JSWSTART : Start conversion of injected channels
bits : 22 - 22 (1 bit)

EXTSEL : External event select for regular group
bits : 24 - 27 (4 bit)

EXTEN : External trigger enable for regular channels
bits : 28 - 29 (2 bit)

SWSTART : Start conversion of regular channels
bits : 30 - 30 (1 bit)


SMPR1

sample time register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR1 SMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPx_x

SMPx_x : Sample time bits
bits : 0 - 31 (32 bit)



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