\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x2C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
TD RUN Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDRUN : TDRUN
bits : 0 - 0 (1 bit)
access : write-only
TD DMA Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMAEN
bits : 0 - 0 (1 bit)
access : read-write
TD RG0 Timer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG : TDRG
bits : 0 - 15 (16 bit)
access : read-write
TD RG1 Timer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG1 : TDRG1
bits : 0 - 15 (16 bit)
access : read-write
TD RG2 Timer Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG2 : TDRG2
bits : 0 - 15 (16 bit)
access : read-write
TD RG3 Timer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG3 : TDRG3
bits : 0 - 15 (16 bit)
access : read-write
TD RG4 Timer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG4 : TDRG4
bits : 0 - 15 (16 bit)
access : read-write
TD CP0 Capture Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG0 : CPRG0
bits : 0 - 15 (16 bit)
access : read-only
TD CP1 Capture Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG1 : CPRG1
bits : 0 - 15 (16 bit)
access : read-only
TD CP2 Capture Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG2 : CPRG2
bits : 0 - 15 (16 bit)
access : read-only
TD CP3 Capture Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG3 : CPRG3
bits : 0 - 15 (16 bit)
access : read-only
TD CP4 Capture Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG4 : CPRG4
bits : 0 - 15 (16 bit)
access : read-only
TD Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDISO : TDISO
bits : 0 - 1 (2 bit)
access : read-write
TDRDE : TDRDE
bits : 2 - 2 (1 bit)
access : read-write
TD Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCLK : TDCLK
bits : 0 - 3 (4 bit)
access : read-write
TDCLE : TDCLE
bits : 4 - 4 (1 bit)
access : read-write
TDIV0 : TDIV0
bits : 6 - 6 (1 bit)
access : read-write
TDIV1 : TDIV1
bits : 7 - 7 (1 bit)
access : read-write
TD Compare Register update control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDSFT : TDSFT
bits : 0 - 0 (1 bit)
access : write-only
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