\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x2C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0xC0 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x110 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x12C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
RUN
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRUN : TDRUN
bits : 0 - 0 (1 bit)
access : write-only
CR
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDISO : TDISO
bits : 0 - 1 (2 bit)
access : read-write
TDRDE : TDRDE
bits : 2 - 2 (1 bit)
access : read-write
TDMDPT10 : TDMDPT10
bits : 4 - 4 (1 bit)
access : read-write
TDMDCY10 : TDMDCY10
bits : 5 - 7 (3 bit)
access : read-write
TDMDPT11 : TDMDPT11
bits : 8 - 8 (1 bit)
access : read-write
TDMDCY11 : TDMDCY11
bits : 9 - 11 (3 bit)
access : read-write
MOD
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCLK : TDCLK
bits : 0 - 2 (3 bit)
access : read-write
TDCLE : TDCLE
bits : 4 - 4 (1 bit)
access : read-write
TDIV0 : TDIV0
bits : 6 - 6 (1 bit)
access : read-write
TDIV1 : TDIV1
bits : 7 - 7 (1 bit)
access : read-write
DMA
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMAEN
bits : 0 - 0 (1 bit)
access : read-write
CP0
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG0 : CPRG0
bits : 0 - 15 (16 bit)
access : read-only
CP1
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG1 : CPRG1
bits : 0 - 15 (16 bit)
access : read-only
CP2
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG2 : CPRG2
bits : 0 - 19 (20 bit)
access : read-only
CP3
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG3 : CPRG3
bits : 0 - 15 (16 bit)
access : read-only
CP4
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPRG4 : CPRG4
bits : 0 - 19 (20 bit)
access : read-only
RG0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG0 : TDRG0
bits : 0 - 15 (16 bit)
access : read-write
RG1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG1 : TDRG1
bits : 0 - 15 (16 bit)
access : read-write
RG2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG2 : TDRG2
bits : 0 - 19 (20 bit)
access : read-write
RG3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG3 : TDRG3
bits : 0 - 15 (16 bit)
access : read-write
RG4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRG4 : TDRG4
bits : 0 - 19 (20 bit)
access : read-write
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