\n

SC3

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0xC Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

EN

BRCR

MOD1

MOD2

BUF

MOD0


EN

EN
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIOE

SIOE : SIOE
bits : 0 - 0 (1 bit)
access : read-write


BRCR

BRCR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRCR BRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR3S BR3CK

BR3S : BR3S
bits : 0 - 3 (4 bit)
access : read-write

BR3CK : BR3CK
bits : 4 - 5 (2 bit)
access : read-write


MOD1

MOD1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD1 MOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SINT TXE FDPX

SINT : SINT
bits : 1 - 3 (3 bit)
access : read-write

TXE : TXE
bits : 4 - 4 (1 bit)
access : read-write

FDPX : FDPX
bits : 5 - 6 (2 bit)
access : read-write


MOD2

MOD2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD2 MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST WBUF DRCHG TXRUN TBEMP

SWRST : SWRST
bits : 0 - 1 (2 bit)
access : read-write

WBUF : WBUF
bits : 2 - 2 (1 bit)
access : read-write

DRCHG : DRCHG
bits : 3 - 3 (1 bit)
access : read-write

TXRUN : TXRUN
bits : 5 - 5 (1 bit)
access : read-only

TBEMP : TBEMP
bits : 7 - 7 (1 bit)
access : read-only


BUF

BUF
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUF BUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB

TB : TB
bits : 0 - 7 (8 bit)
access : read-write


MOD0

MOD0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD0 MOD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC SM

SC : SC
bits : 0 - 1 (2 bit)
access : read-write

SM : SM
bits : 2 - 3 (2 bit)
access : read-write



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