\n

SIOR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

EN

CR0

CR1


EN

EN
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIOREN

SIOREN : SIOREN
bits : 0 - 0 (1 bit)
access : read-write


CR0

CR0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIORCR

SIORCR : SIORCR
bits : 0 - 0 (1 bit)
access : read-write


CR1

CR1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIOM SIOPH UARTPH SIOACK UARTACK

SIOM : SIOM
bits : 0 - 0 (1 bit)
access : read-write

SIOPH : SIOPH
bits : 2 - 2 (1 bit)
access : read-write

UARTPH : UARTPH
bits : 3 - 3 (1 bit)
access : read-write

SIOACK : SIOACK
bits : 4 - 5 (2 bit)
access : read-write

UARTACK : UARTACK
bits : 6 - 7 (2 bit)
access : read-write



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