\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x3C Bytes (0x0)
size : 0xC4 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x108 Bytes (0x0)
size : 0x6EF8 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x7000 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x7010 Bytes (0x0)
size : 0xF0 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x7100 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Accumulator
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Lower Limit Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : START
bits : 16 - 16 (1 bit)
access : read-write
STEP : STEP
bits : 24 - 24 (1 bit)
access : read-write
BRK : BRK
bits : 25 - 25 (1 bit)
access : read-write
Flag Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER : OVER
bits : 16 - 16 (1 bit)
access : read-write
UNDER : UNDER
bits : 17 - 17 (1 bit)
access : read-write
ZERO : ZERO
bits : 24 - 24 (1 bit)
access : read-write
Add Sub Value Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Add Sub Value Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Arithmetic Parameter with Signed Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA0 : SA0
bits : 16 - 16 (1 bit)
access : read-write
SM0 : SM0
bits : 17 - 17 (1 bit)
access : read-write
SM1 : SM1
bits : 18 - 18 (1 bit)
access : read-write
SL0 : SL0
bits : 19 - 19 (1 bit)
access : read-write
SL1 : SL1
bits : 20 - 20 (1 bit)
access : read-write
SR0 : SR0
bits : 21 - 21 (1 bit)
access : read-write
SR1 : SR1
bits : 22 - 22 (1 bit)
access : read-write
Address Pointer 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Pointer 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Pointer 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Pointer 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Break Pointer
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Program Counter
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Repeat Processing Vector Pointer
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Multiplier Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Run Trigger Enable Register
address_offset : 0x7000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : INTEN0
bits : 0 - 0 (1 bit)
access : read-write
INTEN1 : INTEN1
bits : 1 - 1 (1 bit)
access : read-write
INTEN2 : INTEN2
bits : 2 - 2 (1 bit)
access : read-write
INTEN3 : INTEN3
bits : 3 - 3 (1 bit)
access : read-write
INTEN4 : INTEN4
bits : 4 - 4 (1 bit)
access : read-write
INTEN5 : INTEN5
bits : 5 - 5 (1 bit)
access : read-write
INTEN6 : INTEN6
bits : 6 - 6 (1 bit)
access : read-write
INTEN7 : INTEN7
bits : 7 - 7 (1 bit)
access : read-write
INTEN8 : INTEN8
bits : 8 - 8 (1 bit)
access : read-write
INTEN9 : INTEN9
bits : 9 - 9 (1 bit)
access : read-write
INTEN10 : INTEN10
bits : 10 - 10 (1 bit)
access : read-write
INTEN11 : INTEN11
bits : 11 - 11 (1 bit)
access : read-write
INTEN12 : INTEN12
bits : 12 - 12 (1 bit)
access : read-write
INTEN13 : INTEN13
bits : 13 - 13 (1 bit)
access : read-write
INTEN14 : INTEN14
bits : 14 - 14 (1 bit)
access : read-write
INTEN15 : INTEN15
bits : 15 - 15 (1 bit)
access : read-write
INTEG0 : INTEG0
bits : 16 - 16 (1 bit)
access : read-write
INTEG1 : INTEG1
bits : 17 - 17 (1 bit)
access : read-write
INTEG2 : INTEG2
bits : 18 - 18 (1 bit)
access : read-write
INTEG3 : INTEG3
bits : 19 - 19 (1 bit)
access : read-write
Run Trigger Flag Register
address_offset : 0x7004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTFLG0 : INTFLG0
bits : 0 - 0 (1 bit)
access : read-only
INTFLG1 : INTFLG1
bits : 1 - 1 (1 bit)
access : read-only
INTFLG2 : INTFLG2
bits : 2 - 2 (1 bit)
access : read-only
INTFLG3 : INTFLG3
bits : 3 - 3 (1 bit)
access : read-only
INTFLG4 : INTFLG4
bits : 4 - 4 (1 bit)
access : read-only
INTFLG5 : INTFLG5
bits : 5 - 5 (1 bit)
access : read-only
INTFLG6 : INTFLG6
bits : 6 - 6 (1 bit)
access : read-only
INTFLG7 : INTFLG7
bits : 7 - 7 (1 bit)
access : read-only
INTFLG8 : INTFLG8
bits : 8 - 8 (1 bit)
access : read-only
INTFLG9 : INTFLG9
bits : 9 - 9 (1 bit)
access : read-only
INTFLG10 : INTFLG10
bits : 10 - 10 (1 bit)
access : read-only
INTFLG11 : INTFLG11
bits : 11 - 11 (1 bit)
access : read-only
INTFLG12 : INTFLG12
bits : 12 - 12 (1 bit)
access : read-only
INTFLG13 : INTFLG13
bits : 13 - 13 (1 bit)
access : read-only
INTFLG14 : INTFLG14
bits : 14 - 14 (1 bit)
access : read-only
INTFLG15 : INTFLG15
bits : 15 - 15 (1 bit)
access : read-only
INTOVRF0 : INTOVRF0
bits : 16 - 16 (1 bit)
access : read-only
INTOVRF1 : INTOVRF1
bits : 17 - 17 (1 bit)
access : read-only
INTOVRF2 : INTOVRF2
bits : 18 - 18 (1 bit)
access : read-only
INTOVRF3 : INTOVRF3
bits : 19 - 19 (1 bit)
access : read-only
INTOVRF4 : INTOVRF4
bits : 20 - 20 (1 bit)
access : read-only
INTOVRF5 : INTOVRF5
bits : 21 - 21 (1 bit)
access : read-only
INTOVRF6 : INTOVRF6
bits : 22 - 22 (1 bit)
access : read-only
INTOVRF7 : INTOVRF7
bits : 23 - 23 (1 bit)
access : read-only
INTOVRF8 : INTOVRF8
bits : 24 - 24 (1 bit)
access : read-only
INTOVRF9 : INTOVRF9
bits : 25 - 25 (1 bit)
access : read-only
INTOVRF10 : INTOVRF10
bits : 26 - 26 (1 bit)
access : read-only
INTOVRF11 : INTOVRF11
bits : 27 - 27 (1 bit)
access : read-only
INTOVRF12 : INTOVRF12
bits : 28 - 28 (1 bit)
access : read-only
INTOVRF13 : INTOVRF13
bits : 29 - 29 (1 bit)
access : read-only
INTOVRF14 : INTOVRF14
bits : 30 - 30 (1 bit)
access : read-only
INTOVRF15 : INTOVRF15
bits : 31 - 31 (1 bit)
access : read-only
Run Trigger Clear Register
address_offset : 0x7008 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTCLR0 : INTCLR0
bits : 0 - 0 (1 bit)
access : write-only
INTCLR1 : INTCLR1
bits : 1 - 1 (1 bit)
access : write-only
INTCLR2 : INTCLR2
bits : 2 - 2 (1 bit)
access : write-only
INTCLR3 : INTCLR3
bits : 3 - 3 (1 bit)
access : write-only
INTCLR4 : INTCLR4
bits : 4 - 4 (1 bit)
access : write-only
INTCLR5 : INTCLR5
bits : 5 - 5 (1 bit)
access : write-only
INTCLR6 : INTCLR6
bits : 6 - 6 (1 bit)
access : write-only
INTCLR7 : INTCLR7
bits : 7 - 7 (1 bit)
access : write-only
INTCLR8 : INTCLR8
bits : 8 - 8 (1 bit)
access : write-only
INTCLR9 : INTCLR9
bits : 9 - 9 (1 bit)
access : write-only
INTCLR10 : INTCLR10
bits : 10 - 10 (1 bit)
access : write-only
INTCLR11 : INTCLR11
bits : 11 - 11 (1 bit)
access : write-only
INTCLR12 : INTCLR12
bits : 12 - 12 (1 bit)
access : write-only
INTCLR13 : INTCLR13
bits : 13 - 13 (1 bit)
access : write-only
INTCLR14 : INTCLR14
bits : 14 - 14 (1 bit)
access : write-only
INTCLR15 : INTCLR15
bits : 15 - 15 (1 bit)
access : write-only
Run Trigger Clear Register
address_offset : 0x700C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTSET0 : INTSET0
bits : 0 - 0 (1 bit)
access : write-only
INTSET1 : INTSET1
bits : 1 - 1 (1 bit)
access : write-only
INTSET2 : INTSET2
bits : 2 - 2 (1 bit)
access : write-only
INTSET3 : INTSET3
bits : 3 - 3 (1 bit)
access : write-only
INTSET4 : INTSET4
bits : 4 - 4 (1 bit)
access : write-only
INTSET5 : INTSET5
bits : 5 - 5 (1 bit)
access : write-only
INTSET6 : INTSET6
bits : 6 - 6 (1 bit)
access : write-only
INTSET7 : INTSET7
bits : 7 - 7 (1 bit)
access : write-only
INTSET8 : INTSET8
bits : 8 - 8 (1 bit)
access : write-only
INTSET9 : INTSET9
bits : 9 - 9 (1 bit)
access : write-only
INTSET10 : INTSET10
bits : 10 - 10 (1 bit)
access : write-only
INTSET11 : INTSET11
bits : 11 - 11 (1 bit)
access : write-only
INTSET12 : INTSET12
bits : 12 - 12 (1 bit)
access : write-only
INTSET13 : INTSET13
bits : 13 - 13 (1 bit)
access : write-only
INTSET14 : INTSET14
bits : 14 - 14 (1 bit)
access : write-only
INTSET15 : INTSET15
bits : 15 - 15 (1 bit)
access : write-only
Port Output Enable Register for PSC
address_offset : 0x7100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCPTO : PSCPTO
bits : 0 - 7 (8 bit)
access : read-write
Port Control Register for PSC
address_offset : 0x7104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCPTC : PSCPTC
bits : 0 - 7 (8 bit)
access : read-write
Port Input Enable Register for PSC
address_offset : 0x7108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PSCPTI : PSCPTI
bits : 0 - 7 (8 bit)
access : read-only
Shift Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Upper Limit Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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