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EPHC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x54 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

EN

ARUN

ACP0

ACP1

ADAT

BRUN

BDMA

BUC

BCAP00

BCAP10

BCAP20

BCAP30

CNT

B0DAT

B1DAT

B2DAT

B3DAT

BCDAT

B0PDT

B1PDT

B2PDT

B3PDT

UPLMT

LWLMT

IE

FLG


EN

EPHC Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SWRST

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

SWRST : SWRST
bits : 6 - 7 (2 bit)
access : write-only


ARUN

EPHC 16-bit Counter Run Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARUN ARUN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN CLR

RUN : RUN
bits : 0 - 0 (1 bit)
access : read-write

CLR : CLR
bits : 1 - 1 (1 bit)
access : read-write


ACP0

EPHC Pulse Counter Compare 0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACP0 ACP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP0

CMP0 : CMP0
bits : 0 - 15 (16 bit)
access : read-write


ACP1

EPHC Pulse Counter Compare 1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACP1 ACP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP1

CMP1 : CMP1
bits : 0 - 15 (16 bit)
access : read-write


ADAT

EPHC 16-bit Counter Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADAT ADAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAT PMF PHCDIRF

DAT : DAT
bits : 0 - 15 (16 bit)
access : read-write

PMF : PMF
bits : 30 - 30 (1 bit)
access : read-only

PHCDIRF : PHCDIRF
bits : 31 - 31 (1 bit)
access : read-only


BRUN

EPHC 24-bit Counter Run Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRUN BRUN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T24RUN

T24RUN : T24RUN
bits : 0 - 0 (1 bit)
access : read-write


BDMA

EPHC DMAE Request Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMA BDMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMADT0 DMADT1

DMADT0 : DMADT0
bits : 0 - 0 (1 bit)
access : read-write

DMADT1 : DMADT1
bits : 1 - 1 (1 bit)
access : read-write


BUC

EPHC 24-bit Counter Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUC BUC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T24UCR

T24UCR : T24UCR
bits : 0 - 23 (24 bit)
access : read-only


BCAP00

EPHC Capture 00 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCAP00 BCAP00 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP00 OVF00

CAP00 : CAP00
bits : 0 - 23 (24 bit)
access : read-only

OVF00 : OVF00
bits : 24 - 24 (1 bit)
access : read-only


BCAP10

EPHC Capture 10 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCAP10 BCAP10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP10 OVF10

CAP10 : CAP10
bits : 0 - 23 (24 bit)
access : read-only

OVF10 : OVF10
bits : 24 - 24 (1 bit)
access : read-only


BCAP20

EPHC Capture 20 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCAP20 BCAP20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP20 OVF20

CAP20 : CAP20
bits : 0 - 23 (24 bit)
access : read-only

OVF20 : OVF20
bits : 24 - 24 (1 bit)
access : read-only


BCAP30

EPHC Capture 30 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCAP30 BCAP30 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP30 OVF30

CAP30 : CAP30
bits : 0 - 23 (24 bit)
access : read-only

OVF30 : OVF30
bits : 24 - 24 (1 bit)
access : read-only


CNT

EPHC Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA1DN MA1UP BRCK PBMOD PBDIR MA12 MA2DIR NF DATSEL LWLMEN UPLMEN LOADLMT

MA1DN : MA1DN
bits : 0 - 2 (3 bit)
access : read-write

MA1UP : MA1UP
bits : 4 - 6 (3 bit)
access : read-write

BRCK : BRCK
bits : 8 - 9 (2 bit)
access : read-write

PBMOD : PBMOD
bits : 10 - 10 (1 bit)
access : read-write

PBDIR : PBDIR
bits : 11 - 11 (1 bit)
access : read-write

MA12 : MA12
bits : 12 - 12 (1 bit)
access : read-write

MA2DIR : MA2DIR
bits : 13 - 13 (1 bit)
access : read-write

NF : NF
bits : 14 - 15 (2 bit)
access : read-write

DATSEL : DATSEL
bits : 16 - 17 (2 bit)
access : read-write

LWLMEN : LWLMEN
bits : 18 - 18 (1 bit)
access : read-write

UPLMEN : UPLMEN
bits : 19 - 19 (1 bit)
access : read-write

LOADLMT : LOADLMT
bits : 20 - 20 (1 bit)
access : write-only


B0DAT

EPHC Cycle 0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B0DAT B0DAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0DAT

B0DAT : B0DAT
bits : 0 - 23 (24 bit)
access : read-only


B1DAT

EPHC Cycle 1 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B1DAT B1DAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B1DAT

B1DAT : B1DAT
bits : 0 - 23 (24 bit)
access : read-only


B2DAT

EPHC Cycle 2 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B2DAT B2DAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B2DAT

B2DAT : B2DAT
bits : 0 - 23 (24 bit)
access : read-only


B3DAT

EPHC Cycle 3 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B3DAT B3DAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3DAT

B3DAT : B3DAT
bits : 0 - 23 (24 bit)
access : read-only


BCDAT

EPHC Cycle Common Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCDAT BCDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCDAT

BCDAT : BCDAT
bits : 0 - 23 (24 bit)
access : read-only


B0PDT

EPHC Phase DifferEPHCe 0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B0PDT B0PDT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0PDT

B0PDT : B0PDT
bits : 0 - 23 (24 bit)
access : read-only


B1PDT

EPHC Phase DifferEPHCe 1 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B1PDT B1PDT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B1PDT

B1PDT : B1PDT
bits : 0 - 23 (24 bit)
access : read-only


B2PDT

EPHC Phase DifferEPHCe 2 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B2PDT B2PDT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B2PDT

B2PDT : B2PDT
bits : 0 - 23 (24 bit)
access : read-only


B3PDT

EPHC Phase DifferEPHCe 3 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

B3PDT B3PDT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3PDT

B3PDT : B3PDT
bits : 0 - 23 (24 bit)
access : read-only


UPLMT

EPHC Upper Cycle Limit Value Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPLMT UPLMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPLMT

UPLMT : UPLMT
bits : 0 - 23 (24 bit)
access : read-write


LWLMT

EPHC Lower Cycle Limit Value Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LWLMT LWLMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LWLMT

LWLMT : LWLMT
bits : 0 - 23 (24 bit)
access : read-write


IE

EPHC Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPCCP0 INTPCCP1 INTPCOVF INTPCUDF INTPCDT0 INTPCDT1 INTPCDT2 INTPCDT3 INTPCDIR INTPCUOVF INTLWLMT INTUPLMT

INTPCCP0 : INTPCCP0
bits : 0 - 0 (1 bit)
access : read-write

INTPCCP1 : INTPCCP1
bits : 1 - 1 (1 bit)
access : read-write

INTPCOVF : INTPCOVF
bits : 2 - 2 (1 bit)
access : read-write

INTPCUDF : INTPCUDF
bits : 3 - 3 (1 bit)
access : read-write

INTPCDT0 : INTPCDT0
bits : 4 - 4 (1 bit)
access : read-write

INTPCDT1 : INTPCDT1
bits : 5 - 5 (1 bit)
access : read-write

INTPCDT2 : INTPCDT2
bits : 6 - 6 (1 bit)
access : read-write

INTPCDT3 : INTPCDT3
bits : 7 - 7 (1 bit)
access : read-write

INTPCDIR : INTPCDIR
bits : 8 - 8 (1 bit)
access : read-write

INTPCUOVF : INTPCUOVF
bits : 9 - 9 (1 bit)
access : read-write

INTLWLMT : INTLWLMT
bits : 10 - 10 (1 bit)
access : read-write

INTUPLMT : INTUPLMT
bits : 11 - 11 (1 bit)
access : read-write


FLG

EPHC Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLG FLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP0F CMP1F OVFF UDFF SB0F SB1F SB2F SB3F DIRF LWLMT UPLMT

CMP0F : CMP0F
bits : 0 - 0 (1 bit)
access : read-write

CMP1F : CMP1F
bits : 1 - 1 (1 bit)
access : read-write

OVFF : OVFF
bits : 2 - 2 (1 bit)
access : read-write

UDFF : UDFF
bits : 3 - 3 (1 bit)
access : read-write

SB0F : SB0F
bits : 4 - 4 (1 bit)
access : read-write

SB1F : SB1F
bits : 5 - 5 (1 bit)
access : read-write

SB2F : SB2F
bits : 6 - 6 (1 bit)
access : read-write

SB3F : SB3F
bits : 7 - 7 (1 bit)
access : read-write

DIRF : DIRF
bits : 8 - 8 (1 bit)
access : read-write

LWLMT : LWLMT
bits : 9 - 9 (1 bit)
access : read-write

UPLMT : UPLMT
bits : 10 - 10 (1 bit)
access : read-write



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