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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x2C Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x3C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

SYSCR

PWMGEAR

FCLKMSKA

FCMSKA

PROTECT

OSCCR

IMCGA

IMCGB

IMCGC

IMCGD

ICRCG

RSTFLG

NMIFLG

STBYCR

PLLSEL


SYSCR

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK FPSEL0 SCOSEL FCSTOP0 FCSTOP1 FCSTOP2 PSCSTOP0 PSCSTOP1 PSCSTOP2 PSCSTOP3

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

FPSEL0 : FPSEL0
bits : 12 - 12 (1 bit)
access : read-write

SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write

FCSTOP0 : FCSTOP0
bits : 18 - 18 (1 bit)
access : read-write

FCSTOP1 : FCSTOP1
bits : 19 - 19 (1 bit)
access : read-write

FCSTOP2 : FCSTOP2
bits : 20 - 20 (1 bit)
access : read-write

PSCSTOP0 : PSCSTOP0
bits : 21 - 21 (1 bit)
access : read-write

PSCSTOP1 : PSCSTOP1
bits : 22 - 22 (1 bit)
access : read-write

PSCSTOP2 : PSCSTOP2
bits : 23 - 23 (1 bit)
access : read-write

PSCSTOP3 : PSCSTOP3
bits : 24 - 24 (1 bit)
access : read-write


PWMGEAR

Timer D Clock Setting Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMGEAR PWMGEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRDACLKEN TMRDBCLKEN TMRDAGEAR TMRDBGEAR

TMRDACLKEN : TMRDACLKEN
bits : 0 - 0 (1 bit)
access : read-write

TMRDBCLKEN : TMRDBCLKEN
bits : 1 - 1 (1 bit)
access : read-write

TMRDAGEAR : TMRDAGEAR
bits : 4 - 5 (2 bit)
access : read-write

TMRDBGEAR : TMRDBGEAR
bits : 6 - 7 (2 bit)
access : read-write


FCLKMSKA

fclk Supply Stop Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCLKMSKA FCLKMSKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ PORTK PORTL PORTM PORTN DMACA DMACB DMACC ADCA ADCB ADCC WDT SIO_UART I2C EPHC0 EPHC1 EPHC2

PORTA : PORTA
bits : 0 - 0 (1 bit)
access : read-write

PORTB : PORTB
bits : 1 - 1 (1 bit)
access : read-write

PORTC : PORTC
bits : 2 - 2 (1 bit)
access : read-write

PORTD : PORTD
bits : 3 - 3 (1 bit)
access : read-write

PORTE : PORTE
bits : 4 - 4 (1 bit)
access : read-write

PORTF : PORTF
bits : 5 - 5 (1 bit)
access : read-write

PORTG : PORTG
bits : 6 - 6 (1 bit)
access : read-write

PORTH : PORTH
bits : 7 - 7 (1 bit)
access : read-write

PORTJ : PORTJ
bits : 8 - 8 (1 bit)
access : read-write

PORTK : PORTK
bits : 9 - 9 (1 bit)
access : read-write

PORTL : PORTL
bits : 10 - 10 (1 bit)
access : read-write

PORTM : PORTM
bits : 11 - 11 (1 bit)
access : read-write

PORTN : PORTN
bits : 12 - 12 (1 bit)
access : read-write

DMACA : DMACA
bits : 13 - 13 (1 bit)
access : read-write

DMACB : DMACB
bits : 14 - 14 (1 bit)
access : read-write

DMACC : DMACC
bits : 15 - 15 (1 bit)
access : read-write

ADCA : ADCA
bits : 16 - 16 (1 bit)
access : read-write

ADCB : ADCB
bits : 17 - 17 (1 bit)
access : read-write

ADCC : ADCC
bits : 18 - 18 (1 bit)
access : read-write

WDT : WDT
bits : 19 - 19 (1 bit)
access : read-write

SIO_UART : SIO_UART
bits : 20 - 20 (1 bit)
access : read-write

I2C : I2C
bits : 21 - 21 (1 bit)
access : read-write

EPHC0 : EPHC0
bits : 23 - 23 (1 bit)
access : read-write

EPHC1 : EPHC1
bits : 24 - 24 (1 bit)
access : read-write

EPHC2 : EPHC2
bits : 25 - 25 (1 bit)
access : read-write


FCMSKA

fc Supply Stop Register A
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCMSKA FCMSKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 TMRB8 TMRB9 TMRBA TMRBB TMRBC TMRBD TMRBE TMRBF TSPI0 TSPI1 TSPI2 TSPI3 TSPI4 EPHC0 EPHC1 EPHC2 FUART

TMRB0 : TMRB0
bits : 0 - 0 (1 bit)
access : read-write

TMRB1 : TMRB1
bits : 1 - 1 (1 bit)
access : read-write

TMRB2 : TMRB2
bits : 2 - 2 (1 bit)
access : read-write

TMRB3 : TMRB3
bits : 3 - 3 (1 bit)
access : read-write

TMRB4 : TMRB4
bits : 4 - 4 (1 bit)
access : read-write

TMRB5 : TMRB5
bits : 5 - 5 (1 bit)
access : read-write

TMRB6 : TMRB6
bits : 6 - 6 (1 bit)
access : read-write

TMRB7 : TMRB7
bits : 7 - 7 (1 bit)
access : read-write

TMRB8 : TMRB8
bits : 8 - 8 (1 bit)
access : read-write

TMRB9 : TMRB9
bits : 9 - 9 (1 bit)
access : read-write

TMRBA : TMRBA
bits : 10 - 10 (1 bit)
access : read-write

TMRBB : TMRBB
bits : 11 - 11 (1 bit)
access : read-write

TMRBC : TMRBC
bits : 12 - 12 (1 bit)
access : read-write

TMRBD : TMRBD
bits : 13 - 13 (1 bit)
access : read-write

TMRBE : TMRBE
bits : 14 - 14 (1 bit)
access : read-write

TMRBF : TMRBF
bits : 15 - 15 (1 bit)
access : read-write

TSPI0 : TSPI0
bits : 16 - 16 (1 bit)
access : read-write

TSPI1 : TSPI1
bits : 17 - 17 (1 bit)
access : read-write

TSPI2 : TSPI2
bits : 18 - 18 (1 bit)
access : read-write

TSPI3 : TSPI3
bits : 19 - 19 (1 bit)
access : read-write

TSPI4 : TSPI4
bits : 20 - 20 (1 bit)
access : read-write

EPHC0 : EPHC0
bits : 21 - 21 (1 bit)
access : read-write

EPHC1 : EPHC1
bits : 22 - 22 (1 bit)
access : read-write

EPHC2 : EPHC2
bits : 23 - 23 (1 bit)
access : read-write

FUART : FUART
bits : 24 - 24 (1 bit)
access : read-write


PROTECT

Protect Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTECT PROTECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGPROTECT

CGPROTECT : CGPROTECT
bits : 0 - 7 (8 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEON WUEF PLL0ON XEN1 PLL1ON WUPTL XEN2 OSCSEL EHOSCSEL WUPSEL2 WUPT

WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

PLL0ON : PLL0ON
bits : 2 - 2 (1 bit)
access : read-write

XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write

PLL1ON : PLL1ON
bits : 10 - 10 (1 bit)
access : read-write

WUPTL : WUPTL
bits : 14 - 15 (2 bit)
access : read-write

XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write

EHOSCSEL : EHOSCSEL
bits : 18 - 18 (1 bit)
access : read-write

WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write

WUPT : WUPT
bits : 20 - 31 (12 bit)
access : read-write


IMCGA

CG Interrupt Mode Control Register A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGA IMCGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT00EN EMST00 EMCG00 INT01EN EMST01 EMCG01 INT02EN EMST02 EMCG02 INT03EN EMST03 EMCG03

INT00EN : INT00EN
bits : 0 - 0 (1 bit)
access : read-write

EMST00 : EMST00
bits : 2 - 3 (2 bit)
access : read-only

EMCG00 : EMCG00
bits : 4 - 6 (3 bit)
access : read-write

INT01EN : INT01EN
bits : 8 - 8 (1 bit)
access : read-write

EMST01 : EMST01
bits : 10 - 11 (2 bit)
access : read-only

EMCG01 : EMCG01
bits : 12 - 14 (3 bit)
access : read-write

INT02EN : INT02EN
bits : 16 - 16 (1 bit)
access : read-write

EMST02 : EMST02
bits : 18 - 19 (2 bit)
access : read-only

EMCG02 : EMCG02
bits : 20 - 22 (3 bit)
access : read-write

INT03EN : INT03EN
bits : 24 - 24 (1 bit)
access : read-write

EMST03 : EMST03
bits : 26 - 27 (2 bit)
access : read-only

EMCG03 : EMCG03
bits : 28 - 30 (3 bit)
access : read-write


IMCGB

CG Interrupt Mode Control Register B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGB IMCGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT04EN EMST04 EMCG04 INT05EN EMST05 EMCG05 INT06EN EMST06 EMCG06 INT07EN EMST07 EMCG07

INT04EN : INT04EN
bits : 0 - 0 (1 bit)
access : read-write

EMST04 : EMST04
bits : 2 - 3 (2 bit)
access : read-only

EMCG04 : EMCG04
bits : 4 - 6 (3 bit)
access : read-write

INT05EN : INT05EN
bits : 8 - 8 (1 bit)
access : read-write

EMST05 : EMST05
bits : 10 - 11 (2 bit)
access : read-only

EMCG05 : EMCG05
bits : 12 - 14 (3 bit)
access : read-write

INT06EN : INT06EN
bits : 16 - 16 (1 bit)
access : read-write

EMST06 : EMST06
bits : 18 - 19 (2 bit)
access : read-only

EMCG06 : EMCG06
bits : 20 - 22 (3 bit)
access : read-write

INT07EN : INT07EN
bits : 24 - 24 (1 bit)
access : read-write

EMST07 : EMST07
bits : 26 - 27 (2 bit)
access : read-only

EMCG07 : EMCG07
bits : 28 - 30 (3 bit)
access : read-write


IMCGC

CG Interrupt Mode Control Register C
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGC IMCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT08EN EMST08 EMCG08 INT09EN EMST09 EMCG09 INT0AEN EMST0A EMCG0A INT0BEN EMST0B EMCG0B

INT08EN : INT08EN
bits : 0 - 0 (1 bit)
access : read-write

EMST08 : EMST08
bits : 2 - 3 (2 bit)
access : read-only

EMCG08 : EMCG08
bits : 4 - 6 (3 bit)
access : read-write

INT09EN : INT09EN
bits : 8 - 8 (1 bit)
access : read-write

EMST09 : EMST09
bits : 10 - 11 (2 bit)
access : read-only

EMCG09 : EMCG09
bits : 12 - 14 (3 bit)
access : read-write

INT0AEN : INT0AEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0A : EMST0A
bits : 18 - 19 (2 bit)
access : read-only

EMCG0A : EMCG0A
bits : 20 - 22 (3 bit)
access : read-write

INT0BEN : INT0BEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0B : EMST0B
bits : 26 - 27 (2 bit)
access : read-only

EMCG0B : EMCG0B
bits : 28 - 30 (3 bit)
access : read-write


IMCGD

CG Interrupt Mode Control Register D
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGD IMCGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0CEN EMST0C EMCG0C INT0DEN EMST0D EMCG0D INT0EEN EMST0E EMCG0E INT0FEN EMST0F EMCG0F

INT0CEN : INT0CEN
bits : 0 - 0 (1 bit)
access : read-write

EMST0C : EMST0C
bits : 2 - 3 (2 bit)
access : read-only

EMCG0C : EMCG0C
bits : 4 - 6 (3 bit)
access : read-write

INT0DEN : INT0DEN
bits : 8 - 8 (1 bit)
access : read-write

EMST0D : EMST0D
bits : 10 - 11 (2 bit)
access : read-only

EMCG0D : EMCG0D
bits : 12 - 14 (3 bit)
access : read-write

INT0EEN : INT0EEN
bits : 16 - 16 (1 bit)
access : read-write

EMST0E : EMST0E
bits : 18 - 19 (2 bit)
access : read-only

EMCG0E : EMCG0E
bits : 20 - 22 (3 bit)
access : read-write

INT0FEN : INT0FEN
bits : 24 - 24 (1 bit)
access : read-write

EMST0F : EMST0F
bits : 26 - 27 (2 bit)
access : read-only

EMCG0F : EMCG0F
bits : 28 - 30 (3 bit)
access : read-write


ICRCG

CG Interrupt Request Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICRCG ICRCG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICRCG

ICRCG : ICRCG
bits : 0 - 3 (4 bit)
access : write-only


RSTFLG

Reset Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFLG RSTFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINRSTF WDTRSTF BUPRSTF SYSRSTF

PINRSTF : PINRSTF
bits : 0 - 0 (1 bit)
access : read-write

WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write

BUPRSTF : BUPRSTF
bits : 3 - 3 (1 bit)
access : read-write

SYSRSTF : SYSRSTF
bits : 4 - 4 (1 bit)
access : read-write


NMIFLG

NMI Flag Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIFLG NMIFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFLG0 NMIFLG2 NMIFLG4

NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only

NMIFLG2 : NMIFLG2
bits : 2 - 2 (1 bit)
access : read-only

NMIFLG4 : NMIFLG4
bits : 4 - 4 (1 bit)
access : read-only


STBYCR

Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY PTKEEP

STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write

PTKEEP : PTKEEP
bits : 17 - 17 (1 bit)
access : read-write


PLLSEL

PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSEL PLLSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL0SEL PLL0SET PLL1SEL PLL1SETL PLL1SETH

PLL0SEL : PLL0SEL
bits : 0 - 0 (1 bit)
access : read-write

PLL0SET : PLL0SET
bits : 1 - 15 (15 bit)
access : read-write

PLL1SEL : PLL1SEL
bits : 16 - 16 (1 bit)
access : read-write

PLL1SETL : PLL1SETL
bits : 17 - 26 (10 bit)
access : read-write

PLL1SETH : PLL1SETH
bits : 28 - 31 (4 bit)
access : read-write



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