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SMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1C Bytes (0x0)
size : 0xE4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x108 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x120 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x128 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x140 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x148 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x160 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

DIRECT_CMD

SRAM_CYCLES0_0

OPMODE0_0

SRAM_CYCLES0_1

OPMODE0_1

SET_CYCLES

SRAM_CYCLES0_2

OPMODE0_2

SRAM_CYCLES0_3

OPMODE0_3

SET_OPMODE

MEMIF_CFG


DIRECT_CMD

SMC Direct Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT_CMD DIRECT_CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TYPE CHIP_SELECT

CMD_TYPE : CMD_TYPE
bits : 21 - 22 (2 bit)
access : write-only

CHIP_SELECT : CHIP_SELECT
bits : 23 - 25 (3 bit)
access : write-only


SRAM_CYCLES0_0

SMC SRAM Cycles Register 0_0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRAM_CYCLES0_0 SRAM_CYCLES0_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_RC T_WC T_CEOE T_WP T_PC T_TR

T_RC : T_RC
bits : 0 - 3 (4 bit)
access : read-only

T_WC : T_WC
bits : 4 - 7 (4 bit)
access : read-only

T_CEOE : T_CEOE
bits : 8 - 10 (3 bit)
access : read-only

T_WP : T_WP
bits : 11 - 13 (3 bit)
access : read-only

T_PC : T_PC
bits : 14 - 16 (3 bit)
access : read-only

T_TR : T_TR
bits : 17 - 19 (3 bit)
access : read-only


OPMODE0_0

SMC Opmode Register 0_0
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPMODE0_0 OPMODE0_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW RD_BL ADV BURST_ALIGN ADDRESS_MATCH

MW : MW
bits : 0 - 1 (2 bit)
access : read-only

RD_BL : RD_BL
bits : 3 - 5 (3 bit)
access : read-only

ADV : ADV
bits : 11 - 11 (1 bit)
access : read-only

BURST_ALIGN : BURST_ALIGN
bits : 13 - 15 (3 bit)
access : read-only

ADDRESS_MATCH : ADDRESS_MATCH
bits : 24 - 31 (8 bit)
access : read-only


SRAM_CYCLES0_1

SMC SRAM Cycles Register 0_1
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRAM_CYCLES0_1 SRAM_CYCLES0_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_RC T_WC T_CEOE T_WP T_PC T_TR

T_RC : T_RC
bits : 0 - 3 (4 bit)
access : read-only

T_WC : T_WC
bits : 4 - 7 (4 bit)
access : read-only

T_CEOE : T_CEOE
bits : 8 - 10 (3 bit)
access : read-only

T_WP : T_WP
bits : 11 - 13 (3 bit)
access : read-only

T_PC : T_PC
bits : 14 - 16 (3 bit)
access : read-only

T_TR : T_TR
bits : 17 - 19 (3 bit)
access : read-only


OPMODE0_1

SMC Opmode Register 0_1
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPMODE0_1 OPMODE0_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW RD_BL ADV ADDRESS_MATCH

MW : MW
bits : 0 - 1 (2 bit)
access : read-only

RD_BL : RD_BL
bits : 3 - 5 (3 bit)
access : read-only

ADV : ADV
bits : 11 - 11 (1 bit)
access : read-only

ADDRESS_MATCH : ADDRESS_MATCH
bits : 24 - 31 (8 bit)
access : read-only


SET_CYCLES

SMC Set Cycles Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SET_CYCLES SET_CYCLES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_T0 SET_T1 SET_T2 SET_T3 SET_T4 SET_T5

SET_T0 : SET_T0
bits : 0 - 3 (4 bit)
access : write-only

SET_T1 : SET_T1
bits : 4 - 7 (4 bit)
access : write-only

SET_T2 : SET_T2
bits : 8 - 10 (3 bit)
access : write-only

SET_T3 : SET_T3
bits : 11 - 13 (3 bit)
access : write-only

SET_T4 : SET_T4
bits : 14 - 16 (3 bit)
access : write-only

SET_T5 : SET_T5
bits : 17 - 19 (3 bit)
access : write-only


SRAM_CYCLES0_2

SMC SRAM Cycles Register 0_2
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRAM_CYCLES0_2 SRAM_CYCLES0_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_RC T_WC T_CEOE T_WP T_PC T_TR

T_RC : T_RC
bits : 0 - 3 (4 bit)
access : read-only

T_WC : T_WC
bits : 4 - 7 (4 bit)
access : read-only

T_CEOE : T_CEOE
bits : 8 - 10 (3 bit)
access : read-only

T_WP : T_WP
bits : 11 - 13 (3 bit)
access : read-only

T_PC : T_PC
bits : 14 - 16 (3 bit)
access : read-only

T_TR : T_TR
bits : 17 - 19 (3 bit)
access : read-only


OPMODE0_2

SMC Opmode Register 0_2
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPMODE0_2 OPMODE0_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW RD_BL ADV ADDRESS_MATCH

MW : MW
bits : 0 - 1 (2 bit)
access : read-only

RD_BL : RD_BL
bits : 3 - 5 (3 bit)
access : read-only

ADV : ADV
bits : 11 - 11 (1 bit)
access : read-only

ADDRESS_MATCH : ADDRESS_MATCH
bits : 24 - 31 (8 bit)
access : read-only


SRAM_CYCLES0_3

SMC SRAM Cycles Register 0_3
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRAM_CYCLES0_3 SRAM_CYCLES0_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_RC T_WC T_CEOE T_WP T_PC T_TR

T_RC : T_RC
bits : 0 - 3 (4 bit)
access : read-only

T_WC : T_WC
bits : 4 - 7 (4 bit)
access : read-only

T_CEOE : T_CEOE
bits : 8 - 10 (3 bit)
access : read-only

T_WP : T_WP
bits : 11 - 13 (3 bit)
access : read-only

T_PC : T_PC
bits : 14 - 16 (3 bit)
access : read-only

T_TR : T_TR
bits : 17 - 19 (3 bit)
access : read-only


OPMODE0_3

SMC Opmode Register 0_3
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPMODE0_3 OPMODE0_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW RD_BL ADV ADDRESS_MATCH

MW : MW
bits : 0 - 1 (2 bit)
access : read-only

RD_BL : RD_BL
bits : 3 - 5 (3 bit)
access : read-only

ADV : ADV
bits : 11 - 11 (1 bit)
access : read-only

ADDRESS_MATCH : ADDRESS_MATCH
bits : 24 - 31 (8 bit)
access : read-only


SET_OPMODE

SMC Set Opmode Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SET_OPMODE SET_OPMODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_MW SET_RD_BL SET_ADV

SET_MW : SET_MW
bits : 0 - 1 (2 bit)
access : write-only

SET_RD_BL : SET_RD_BL
bits : 3 - 5 (3 bit)
access : write-only

SET_ADV : SET_ADV
bits : 11 - 11 (1 bit)
access : write-only


MEMIF_CFG

SMC Memory Interface Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEMIF_CFG MEMIF_CFG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMORY_TYPE MEMORY_CHIPS MEMORY_WIDTH

MEMORY_TYPE : MEMORY_TYPE
bits : 0 - 1 (2 bit)
access : read-only

MEMORY_CHIPS : MEMORY_CHIPS
bits : 2 - 3 (2 bit)
access : read-only

MEMORY_WIDTH : MEMORY_WIDTH
bits : 4 - 5 (2 bit)
access : read-only



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