\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
Encoder Input Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDEV : ENDEV
bits : 0 - 2 (3 bit)
access : read-write
INTEN : INTEN
bits : 3 - 3 (1 bit)
access : read-write
NR : NR
bits : 4 - 5 (2 bit)
access : read-write
ENRUN : ENRUN
bits : 6 - 6 (1 bit)
access : read-write
ZEN : ZEN
bits : 7 - 7 (1 bit)
access : read-write
CMPEN : CMPEN
bits : 8 - 8 (1 bit)
access : read-write
ZESEL : ZESEL
bits : 9 - 9 (1 bit)
access : read-write
ENCLR : ENCLR
bits : 10 - 10 (1 bit)
access : write-only
SFTCAP : SFTCAP
bits : 11 - 11 (1 bit)
access : write-only
ZDET : ZDET
bits : 12 - 12 (1 bit)
access : read-only
UD : UD
bits : 13 - 13 (1 bit)
access : read-only
REVERR : REVERR
bits : 14 - 14 (1 bit)
access : read-only
CMP : CMP
bits : 15 - 15 (1 bit)
access : read-only
P3EN : P3EN
bits : 16 - 16 (1 bit)
access : read-write
MODE : MODE
bits : 17 - 18 (2 bit)
access : read-write
Encoder Counter Reload Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : RELOAD
bits : 0 - 15 (16 bit)
access : read-write
Encoder Compare Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : INT
bits : 0 - 23 (24 bit)
access : read-write
Encoder Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 23 (24 bit)
access : read-write
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