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OFD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

CR1

MXPLLOFF

MXPLLON

CR2

MNPLLOFF

MNPLLON


CR1

OFD Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDWEN0 OFDWEN1 OFDWEN2 OFDWEN3 OFDWEN4 OFDWEN5 OFDWEN6 OFDWEN7

OFDWEN0 : OFDWEN0
bits : 0 - 0 (1 bit)
access : read-write

OFDWEN1 : OFDWEN1
bits : 1 - 1 (1 bit)
access : read-write

OFDWEN2 : OFDWEN2
bits : 2 - 2 (1 bit)
access : read-write

OFDWEN3 : OFDWEN3
bits : 3 - 3 (1 bit)
access : read-write

OFDWEN4 : OFDWEN4
bits : 4 - 4 (1 bit)
access : read-write

OFDWEN5 : OFDWEN5
bits : 5 - 5 (1 bit)
access : read-write

OFDWEN6 : OFDWEN6
bits : 6 - 6 (1 bit)
access : read-write

OFDWEN7 : OFDWEN7
bits : 7 - 7 (1 bit)
access : read-write


MXPLLOFF

OFD Higher Detection Frequency Setting Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLLOFF MXPLLOFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDMXPLLOFF

OFDMXPLLOFF : OFDMXPLLOFF
bits : 0 - 8 (9 bit)
access : read-write


MXPLLON

OFD Higher Detection Frequency Setting Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MXPLLON MXPLLON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDMXPLLON

OFDMXPLLON : OFDMXPLLON
bits : 0 - 8 (9 bit)
access : read-write


CR2

OFD Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDEN0 OFDEN1 OFDEN2 OFDEN3 OFDEN4 OFDEN5 OFDEN6 OFDEN7

OFDEN0 : OFDEN0
bits : 0 - 0 (1 bit)
access : read-write

OFDEN1 : OFDEN1
bits : 1 - 1 (1 bit)
access : read-write

OFDEN2 : OFDEN2
bits : 2 - 2 (1 bit)
access : read-write

OFDEN3 : OFDEN3
bits : 3 - 3 (1 bit)
access : read-write

OFDEN4 : OFDEN4
bits : 4 - 4 (1 bit)
access : read-write

OFDEN5 : OFDEN5
bits : 5 - 5 (1 bit)
access : read-write

OFDEN6 : OFDEN6
bits : 6 - 6 (1 bit)
access : read-write

OFDEN7 : OFDEN7
bits : 7 - 7 (1 bit)
access : read-write


MNPLLOFF

OFD Lower Detection Frequency Setting Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MNPLLOFF MNPLLOFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDMNPLLOFF

OFDMNPLLOFF : OFDMNPLLOFF
bits : 0 - 8 (9 bit)
access : read-write


MNPLLON

OFD Lower Detection Frequency Setting Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MNPLLON MNPLLON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFDMNPLLON

OFDMNPLLON : OFDMNPLLON
bits : 0 - 8 (9 bit)
access : read-write



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