\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x14 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write
PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write
FPSEL : FPSEL
bits : 12 - 12 (1 bit)
access : read-write
CG Interrupt Request Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only
NMI Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only
Reset Flag Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PONRSTF : PONRSTF
bits : 0 - 0 (1 bit)
access : read-write
PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write
WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write
VLTDRSTF : VLTDRSTF
bits : 3 - 3 (1 bit)
access : read-write
DBGRSTF : DBGRSTF
bits : 4 - 4 (1 bit)
access : read-write
OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write
CG Interrupt Mode Control Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0EN : INT0EN
bits : 0 - 0 (1 bit)
access : read-write
EMST0 : EMST0
bits : 2 - 3 (2 bit)
access : read-only
EMCG0 : EMCG0
bits : 4 - 6 (3 bit)
access : read-write
INT1EN : INT1EN
bits : 8 - 8 (1 bit)
access : read-write
EMST1 : EMST1
bits : 10 - 11 (2 bit)
access : read-only
EMCG1 : EMCG1
bits : 12 - 14 (3 bit)
access : read-write
INT2EN : INT2EN
bits : 16 - 16 (1 bit)
access : read-write
EMST2 : EMST2
bits : 18 - 19 (2 bit)
access : read-only
EMCG2 : EMCG2
bits : 20 - 22 (3 bit)
access : read-write
Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only
WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only
PLLON : PLLON
bits : 2 - 2 (1 bit)
access : read-write
WUPSEL1 : WUPSEL1
bits : 3 - 3 (1 bit)
access : read-write
XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write
XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write
OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write
HOSCON : HOSCON
bits : 18 - 18 (1 bit)
access : read-write
WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write
WU0DR : WU0DR
bits : 20 - 31 (12 bit)
access : read-write
Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write
RXEN : RXEN
bits : 8 - 8 (1 bit)
access : read-write
DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write
PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSEL : PLLSEL
bits : 0 - 0 (1 bit)
access : read-write
PLLSET0 : PLLSET0
bits : 1 - 10 (10 bit)
access : read-write
PLLSET1 : PLLSET1
bits : 12 - 15 (4 bit)
access : read-write
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