\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x8 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x24 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x48 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 7 (8 bit)
access : read-write
FE : FE
bits : 8 - 8 (1 bit)
access : read-only
PE : PE
bits : 9 - 9 (1 bit)
access : read-only
BE : BE
bits : 10 - 10 (1 bit)
access : read-only
OE : OE
bits : 11 - 11 (1 bit)
access : read-only
Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : BUSY
bits : 3 - 3 (1 bit)
access : read-only
RXFE : RXFE
bits : 4 - 4 (1 bit)
access : read-only
TXFF : TXFF
bits : 5 - 5 (1 bit)
access : read-only
RXFF : RXFF
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
Integer Baud Rate Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUDDIVINT : BAUDDIVINT
bits : 0 - 15 (16 bit)
access : read-write
Fractional Baud Rate Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUDDIVFRAC : BAUDDIVFRAC
bits : 0 - 5 (6 bit)
access : read-write
Line Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : BRK
bits : 0 - 0 (1 bit)
access : read-write
PEN : PEN
bits : 1 - 1 (1 bit)
access : read-write
EPS : EPS
bits : 2 - 2 (1 bit)
access : read-write
STP2 : STP2
bits : 3 - 3 (1 bit)
access : read-write
FEN : FEN
bits : 4 - 4 (1 bit)
access : read-write
WLEN : WLEN
bits : 5 - 6 (2 bit)
access : read-write
SPS : SPS
bits : 7 - 7 (1 bit)
access : read-write
Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : UARTEN
bits : 0 - 0 (1 bit)
access : read-write
TXE : TXE
bits : 8 - 8 (1 bit)
access : read-write
RXE : RXE
bits : 9 - 9 (1 bit)
access : read-write
Interrupt FIFO Level Selection Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXIFLSEL : TXIFLSEL
bits : 0 - 2 (3 bit)
access : read-write
RXIFLSEL : RXIFLSEL
bits : 3 - 5 (3 bit)
access : read-write
Interrupt Mask Set_Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIM : RXIM
bits : 4 - 4 (1 bit)
access : read-write
TXIM : TXIM
bits : 5 - 5 (1 bit)
access : read-write
RTIM : RTIM
bits : 6 - 6 (1 bit)
access : read-write
FEIM : FEIM
bits : 7 - 7 (1 bit)
access : read-write
PEIM : PEIM
bits : 8 - 8 (1 bit)
access : read-write
BEIM : BEIM
bits : 9 - 9 (1 bit)
access : read-write
OEIM : OEIM
bits : 10 - 10 (1 bit)
access : read-write
Raw Interrupt Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRIS : RXRIS
bits : 4 - 4 (1 bit)
access : read-only
TXRIS : TXRIS
bits : 5 - 5 (1 bit)
access : read-only
RTRIS : RTRIS
bits : 6 - 6 (1 bit)
access : read-only
FERIS : FERIS
bits : 7 - 7 (1 bit)
access : read-only
PERIS : PERIS
bits : 8 - 8 (1 bit)
access : read-only
BERIS : BERIS
bits : 9 - 9 (1 bit)
access : read-only
OERIS : OERIS
bits : 10 - 10 (1 bit)
access : read-only
Receive Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FE : FE
bits : 0 - 0 (1 bit)
access : read-only
PE : PE
bits : 1 - 1 (1 bit)
access : read-only
BE : BE
bits : 2 - 2 (1 bit)
access : read-only
OE : OE
bits : 3 - 3 (1 bit)
access : read-only
Error Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FE : FE
bits : 0 - 0 (1 bit)
access : write-only
PE : PE
bits : 1 - 1 (1 bit)
access : write-only
BE : BE
bits : 2 - 2 (1 bit)
access : write-only
OE : OE
bits : 3 - 3 (1 bit)
access : write-only
Masked Interrupt Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXMIS : RXMIS
bits : 4 - 4 (1 bit)
access : read-only
TXMIS : TXMIS
bits : 5 - 5 (1 bit)
access : read-only
RTMIS : RTMIS
bits : 6 - 6 (1 bit)
access : read-only
FEMIS : FEMIS
bits : 7 - 7 (1 bit)
access : read-only
PEMIS : PEMIS
bits : 8 - 8 (1 bit)
access : read-only
BEMIS : BEMIS
bits : 9 - 9 (1 bit)
access : read-only
OEMIS : OEMIS
bits : 10 - 10 (1 bit)
access : read-only
Interrupt Clear Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXIC : RXIC
bits : 4 - 4 (1 bit)
access : write-only
TXIC : TXIC
bits : 5 - 5 (1 bit)
access : write-only
RTIC : RTIC
bits : 6 - 6 (1 bit)
access : write-only
FEIC : FEIC
bits : 7 - 7 (1 bit)
access : write-only
PEIC : PEIC
bits : 8 - 8 (1 bit)
access : write-only
BEIC : BEIC
bits : 9 - 9 (1 bit)
access : write-only
OEIC : OEIC
bits : 10 - 10 (1 bit)
access : write-only
HC Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCCR : HCCR
bits : 0 - 0 (1 bit)
access : read-write
HCMD : HCMD
bits : 1 - 1 (1 bit)
access : read-write
HCST : HCST
bits : 2 - 2 (1 bit)
access : read-write
HCZR : HCZR
bits : 4 - 6 (3 bit)
access : read-write
HCLB : HCLB
bits : 7 - 7 (1 bit)
access : read-write
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