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CG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :

Registers

SYSCR

CKSEL

ICRCG

NMIFLG

RSTFLG

IMCGA

IMCGB

IMCGC

IMCGD

IMCGE

OSCCR

STBYCR

PLLSEL


SYSCR

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCR SYSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEAR PRCK FPSEL SCOSEL FCSTOP

GEAR : GEAR
bits : 0 - 2 (3 bit)
access : read-write

PRCK : PRCK
bits : 8 - 10 (3 bit)
access : read-write

FPSEL : FPSEL
bits : 12 - 13 (2 bit)
access : read-write

SCOSEL : SCOSEL
bits : 16 - 17 (2 bit)
access : read-write

FCSTOP : FCSTOP
bits : 20 - 20 (1 bit)
access : read-write


CKSEL

System Clock Selection Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKSEL CKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCKFLG SYSCK

SYSCKFLG : SYSCKFLG
bits : 0 - 0 (1 bit)
access : read-only

SYSCK : SYSCK
bits : 1 - 1 (1 bit)
access : read-write


ICRCG

CG Interrupt Request Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICRCG ICRCG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICRCG

ICRCG : ICRCG
bits : 0 - 4 (5 bit)
access : write-only


NMIFLG

NMI Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NMIFLG NMIFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFLG0 NMIFLG2

NMIFLG0 : NMIFLG0
bits : 0 - 0 (1 bit)
access : read-only

NMIFLG2 : NMIFLG2
bits : 2 - 2 (1 bit)
access : read-only


RSTFLG

Reset Flag Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFLG RSTFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONRSTF PINRSTF WDTRSTF DBGRSTF OFDRSTF

PONRSTF : PONRSTF
bits : 0 - 0 (1 bit)
access : read-write

PINRSTF : PINRSTF
bits : 1 - 1 (1 bit)
access : read-write

WDTRSTF : WDTRSTF
bits : 2 - 2 (1 bit)
access : read-write

DBGRSTF : DBGRSTF
bits : 4 - 4 (1 bit)
access : read-write

OFDRSTF : OFDRSTF
bits : 5 - 5 (1 bit)
access : read-write


IMCGA

CG Interrupt Mode Control Register A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGA IMCGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT0EN EMST0 EMCG0 INT1EN EMST1 EMCG1 INT2EN EMST2 EMCG2 INT3EN EMST3 EMCG3

INT0EN : INT0EN
bits : 0 - 0 (1 bit)
access : read-write

EMST0 : EMST0
bits : 2 - 3 (2 bit)
access : read-only

EMCG0 : EMCG0
bits : 4 - 6 (3 bit)
access : read-write

INT1EN : INT1EN
bits : 8 - 8 (1 bit)
access : read-write

EMST1 : EMST1
bits : 10 - 11 (2 bit)
access : read-only

EMCG1 : EMCG1
bits : 12 - 14 (3 bit)
access : read-write

INT2EN : INT2EN
bits : 16 - 16 (1 bit)
access : read-write

EMST2 : EMST2
bits : 18 - 19 (2 bit)
access : read-only

EMCG2 : EMCG2
bits : 20 - 22 (3 bit)
access : read-write

INT3EN : INT3EN
bits : 24 - 24 (1 bit)
access : read-write

EMST3 : EMST3
bits : 26 - 27 (2 bit)
access : read-only

EMCG3 : EMCG3
bits : 28 - 30 (3 bit)
access : read-write


IMCGB

CG Interrupt Mode Control Register B
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGB IMCGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT4EN EMST4 EMCG4 INT5EN EMST5 EMCG5

INT4EN : INT4EN
bits : 0 - 0 (1 bit)
access : read-write

EMST4 : EMST4
bits : 2 - 3 (2 bit)
access : read-only

EMCG4 : EMCG4
bits : 4 - 6 (3 bit)
access : read-write

INT5EN : INT5EN
bits : 8 - 8 (1 bit)
access : read-write

EMST5 : EMST5
bits : 10 - 11 (2 bit)
access : read-only

EMCG5 : EMCG5
bits : 12 - 14 (3 bit)
access : read-write


IMCGC

CG Interrupt Mode Control Register C
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGC IMCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT8EN EMST8 EMCG8

INT8EN : INT8EN
bits : 0 - 0 (1 bit)
access : read-write

EMST8 : EMST8
bits : 2 - 3 (2 bit)
access : read-only

EMCG8 : EMCG8
bits : 4 - 6 (3 bit)
access : read-write


IMCGD

CG Interrupt Mode Control Register D
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGD IMCGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTFEN EMSTF EMCGF

INTFEN : INTFEN
bits : 24 - 24 (1 bit)
access : read-write

EMSTF : EMSTF
bits : 26 - 27 (2 bit)
access : read-only

EMCGF : EMCGF
bits : 28 - 30 (3 bit)
access : read-write


IMCGE

CG Interrupt Mode Control Register E
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMCGE IMCGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRTCEN EMSTRTCT EMCGRTC INTRMCRXEN EMSTRMCRX EMCGRMCRX

INTRTCEN : INTRTCEN
bits : 0 - 0 (1 bit)
access : read-write

EMSTRTCT : EMSTRTCT
bits : 2 - 3 (2 bit)
access : read-only

EMCGRTC : EMCGRTC
bits : 4 - 6 (3 bit)
access : read-write

INTRMCRXEN : INTRMCRXEN
bits : 8 - 8 (1 bit)
access : read-write

EMSTRMCRX : EMSTRMCRX
bits : 10 - 11 (2 bit)
access : read-only

EMCGRMCRX : EMCGRMCRX
bits : 12 - 14 (3 bit)
access : read-write


OSCCR

Oscillation Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCR OSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEON WUEF PLLON WUPSEL1 XEN1 XTEN WUODR0 WUODR1 XEN2 OSCSEL HOSCON WUPSEL2 WUODR2 WUODR3 WUODR4 WUODR5 WUODR6 WUODR7 WUODR8 WUODR9 WUODR10 WUODR11 WUODR12 WUODR13

WUEON : WUEON
bits : 0 - 0 (1 bit)
access : write-only

WUEF : WUEF
bits : 1 - 1 (1 bit)
access : read-only

PLLON : PLLON
bits : 2 - 2 (1 bit)
access : read-write

WUPSEL1 : WUPSEL1
bits : 3 - 3 (1 bit)
access : read-write

XEN1 : XEN1
bits : 8 - 8 (1 bit)
access : read-write

XTEN : XTEN
bits : 9 - 9 (1 bit)
access : read-write

WUODR0 : WUODR0
bits : 14 - 14 (1 bit)
access : read-write

WUODR1 : WUODR1
bits : 15 - 15 (1 bit)
access : read-write

XEN2 : XEN2
bits : 16 - 16 (1 bit)
access : read-write

OSCSEL : OSCSEL
bits : 17 - 17 (1 bit)
access : read-write

HOSCON : HOSCON
bits : 18 - 18 (1 bit)
access : read-write

WUPSEL2 : WUPSEL2
bits : 19 - 19 (1 bit)
access : read-write

WUODR2 : WUODR2
bits : 20 - 20 (1 bit)
access : read-write

WUODR3 : WUODR3
bits : 21 - 21 (1 bit)
access : read-write

WUODR4 : WUODR4
bits : 22 - 22 (1 bit)
access : read-write

WUODR5 : WUODR5
bits : 23 - 23 (1 bit)
access : read-write

WUODR6 : WUODR6
bits : 24 - 24 (1 bit)
access : read-write

WUODR7 : WUODR7
bits : 25 - 25 (1 bit)
access : read-write

WUODR8 : WUODR8
bits : 26 - 26 (1 bit)
access : read-write

WUODR9 : WUODR9
bits : 27 - 27 (1 bit)
access : read-write

WUODR10 : WUODR10
bits : 28 - 28 (1 bit)
access : read-write

WUODR11 : WUODR11
bits : 29 - 29 (1 bit)
access : read-write

WUODR12 : WUODR12
bits : 30 - 30 (1 bit)
access : read-write

WUODR13 : WUODR13
bits : 31 - 31 (1 bit)
access : read-write


STBYCR

Standby Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STBYCR STBYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STBY RXEN RXTEN DRVE

STBY : STBY
bits : 0 - 2 (3 bit)
access : read-write

RXEN : RXEN
bits : 8 - 8 (1 bit)
access : read-write

RXTEN : RXTEN
bits : 9 - 9 (1 bit)
access : read-write

DRVE : DRVE
bits : 16 - 16 (1 bit)
access : read-write


PLLSEL

PLL Selection Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSEL PLLSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSEL

PLLSEL : PLLSEL
bits : 0 - 0 (1 bit)
access : read-write



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