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MTPD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x3C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x44 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : reserved
protection :

address_offset : 0x58 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

MDEN

MDCNT

MDPRD

CMPU

CMPV

CMPW

MDOUT

MDPOT

EMGREL

EMGCR

EMGSTA

PORTMD

DTR

TRGCMP0

TRGCMP1

TRGCR

TRGMD

MDCR

CNTSTA


MDEN

PMD Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDEN MDEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMEN

PWMEN : PWMEN
bits : 0 - 0 (1 bit)
access : read-write


MDCNT

PWM Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MDCNT MDCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDCNT

MDCNT : MDCNT
bits : 0 - 0 (1 bit)
access : read-only


MDPRD

PWM Period Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDPRD MDPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDPRD

MDPRD : MDPRD
bits : 0 - 14 (15 bit)
access : read-write


CMPU

PWM Compare Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPU CMPU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPU

CMPU : CMPU
bits : 0 - 14 (15 bit)
access : read-write


CMPV

PWM Compare Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPV CMPV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPV

CMPV : CMPV
bits : 0 - 14 (15 bit)
access : read-write


CMPW

PWM Compare Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPW CMPW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPW

CMPW : CMPW
bits : 0 - 14 (15 bit)
access : read-write


MDOUT

PMD Output Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDOUT MDOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UOC VOC WOC UPWM VPWM WPWM

UOC : UOC
bits : 0 - 1 (2 bit)
access : read-write

VOC : VOC
bits : 2 - 3 (2 bit)
access : read-write

WOC : WOC
bits : 4 - 5 (2 bit)
access : read-write

UPWM : UPWM
bits : 8 - 8 (1 bit)
access : read-write

VPWM : VPWM
bits : 9 - 9 (1 bit)
access : read-write

WPWM : WPWM
bits : 10 - 10 (1 bit)
access : read-write


MDPOT

PMD Output Setting Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDPOT MDPOT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSYNCS POLL POLH

PSYNCS : PSYNCS
bits : 0 - 1 (2 bit)
access : read-write

POLL : POLL
bits : 2 - 2 (1 bit)
access : read-write

POLH : POLH
bits : 3 - 3 (1 bit)
access : read-write


EMGREL

EMG Release Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EMGREL EMGREL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMGREL

EMGREL : EMGREL
bits : 0 - 7 (8 bit)
access : write-only


EMGCR

EMG Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMGCR EMGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMGEN EMGRS EMGMD INHEN EMGCNT

EMGEN : EMGEN
bits : 0 - 0 (1 bit)
access : read-write

EMGRS : EMGRS
bits : 1 - 1 (1 bit)
access : write-only

EMGMD : EMGMD
bits : 3 - 4 (2 bit)
access : read-write

INHEN : INHEN
bits : 5 - 5 (1 bit)
access : read-write

EMGCNT : EMGCNT
bits : 8 - 11 (4 bit)
access : read-write


EMGSTA

EMG Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EMGSTA EMGSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMGST EMGI

EMGST : EMGST
bits : 0 - 0 (1 bit)
access : read-only

EMGI : EMGI
bits : 1 - 1 (1 bit)
access : read-only


PORTMD

Port Output Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTMD PORTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTMD

PORTMD : PORTMD
bits : 0 - 1 (2 bit)
access : read-write


DTR

Dead Time Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTR DTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTR

DTR : DTR
bits : 0 - 7 (8 bit)
access : read-write


TRGCMP0

Trigger Compare Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCMP0 TRGCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGCMP0

TRGCMP0 : TRGCMP0
bits : 0 - 15 (16 bit)
access : read-write


TRGCMP1

Trigger Compare Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCMP1 TRGCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGCMP1

TRGCMP1 : TRGCMP1
bits : 0 - 15 (16 bit)
access : read-write


TRGCR

Trigger Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCR TRGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRG0MD TRG0BE TRG1MD TRG1BE

TRG0MD : TRG0MD
bits : 0 - 2 (3 bit)
access : read-write

TRG0BE : TRG0BE
bits : 3 - 3 (1 bit)
access : read-write

TRG1MD : TRG1MD
bits : 4 - 6 (3 bit)
access : read-write

TRG1BE : TRG1BE
bits : 7 - 7 (1 bit)
access : read-write


TRGMD

Trigger Output Mode Setting Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMD TRGMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMGTGE

EMGTGE : EMGTGE
bits : 0 - 0 (1 bit)
access : read-write


MDCR

PMD Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDCR MDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMMD INTPRD PINT DTYMD SYNTMD PWMCK

PWMMD : PWMMD
bits : 0 - 0 (1 bit)
access : read-write

INTPRD : INTPRD
bits : 1 - 2 (2 bit)
access : read-write

PINT : PINT
bits : 3 - 3 (1 bit)
access : read-write

DTYMD : DTYMD
bits : 4 - 4 (1 bit)
access : read-write

SYNTMD : SYNTMD
bits : 5 - 5 (1 bit)
access : read-write

PWMCK : PWMCK
bits : 6 - 6 (1 bit)
access : read-write


CNTSTA

PWM Counter Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNTSTA CNTSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDWN

UPDWN : UPDWN
bits : 0 - 0 (1 bit)
access : read-only



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