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SSP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :

Registers

CR0

CPSR

IMSC

RIS

MIS

ICR

DMACR

CR1

DR

SR


CR0

SSP Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSS FRF SPO SPH SCR

DSS : DSS
bits : 0 - 3 (4 bit)
access : read-write

FRF : FRF
bits : 4 - 5 (2 bit)
access : read-write

SPO : SPO
bits : 6 - 6 (1 bit)
access : read-write

SPH : SPH
bits : 7 - 7 (1 bit)
access : read-write

SCR : SCR
bits : 8 - 15 (8 bit)
access : read-write


CPSR

SSP Clock Prescaler Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSDVSR

CPSDVSR : CPSDVSR
bits : 0 - 7 (8 bit)
access : read-write


IMSC

SSP Interrupt Mask Set and Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMSC IMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIM RTIM RXIM TXIM

RORIM : RORIM
bits : 0 - 0 (1 bit)
access : read-write

RTIM : RTIM
bits : 1 - 1 (1 bit)
access : read-write

RXIM : RXIM
bits : 2 - 2 (1 bit)
access : read-write

TXIM : TXIM
bits : 3 - 3 (1 bit)
access : read-write


RIS

SSP Raw Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORRIS RTRIS RXRIS TXRIS

RORRIS : RORRIS
bits : 0 - 0 (1 bit)
access : read-only

RTRIS : RTRIS
bits : 1 - 1 (1 bit)
access : read-only

RXRIS : RXRIS
bits : 2 - 2 (1 bit)
access : read-only

TXRIS : TXRIS
bits : 3 - 3 (1 bit)
access : read-only


MIS

SSP Masked Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORMIS RTMIS RXMIS TXMIS

RORMIS : RORMIS
bits : 0 - 0 (1 bit)
access : read-only

RTMIS : RTMIS
bits : 1 - 1 (1 bit)
access : read-only

RXMIS : RXMIS
bits : 2 - 2 (1 bit)
access : read-only

TXMIS : TXMIS
bits : 3 - 3 (1 bit)
access : read-only


ICR

SSP Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIC RTIC

RORIC : RORIC
bits : 0 - 0 (1 bit)
access : write-only

RTIC : RTIC
bits : 1 - 1 (1 bit)
access : write-only


DMACR

SSP DMA Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE

RXDMAE : RXDMAE
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : TXDMAE
bits : 1 - 1 (1 bit)
access : read-write


CR1

SSP Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM SSE MS SOD

LBM : LBM
bits : 0 - 0 (1 bit)
access : read-write

SSE : SSE
bits : 1 - 1 (1 bit)
access : read-write

MS : MS
bits : 2 - 2 (1 bit)
access : read-write

SOD : SOD
bits : 3 - 3 (1 bit)
access : read-write


DR

SSP Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 15 (16 bit)
access : read-write


SR

SSP Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TNF RNE RFF BSY

TFE : TFE
bits : 0 - 0 (1 bit)
access : read-only

TNF : TNF
bits : 1 - 1 (1 bit)
access : read-only

RNE : RNE
bits : 2 - 2 (1 bit)
access : read-only

RFF : RFF
bits : 3 - 3 (1 bit)
access : read-only

BSY : BSY
bits : 4 - 4 (1 bit)
access : read-only



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